Radio Shack TRS-80 Service Manual page 20

TECHNICAL DESCRIPTION
The techniul description of the Model III Computer CPU
circuit board will be broken down inlo nine sections. These
ilIre:
1. Processor
2.
RAM
3. Adress Decoding
4. Video
5. Video Sync Circuits
6.
Keyboard
7. Cilssette Interfaces
8. Line Printer and Real Time Clock
9_ 1/0 Bus
This breakdown, which follows the partitioning of the sche-
matic diagrams, will allow ea'iY explanation and referencing.
VIDEO SYNC CIRCUITS
The video sync circuits are required 10 meet the pulse width
end polarity requilements of the video monitor. It alo;o allows
adjustment in both the horizontal and vertical planes in dis·
crete increments. The verticol sync pulse VSYNC is active
low and approximately 693J,LSec in duration, The frame late
is either 50 or 60 Hertl. The horizontal rate is 15.840 Hz and
the signal HSYNC
is
active high with a duration of approxi-
mately 8 psec. The vertical plane adjustml!rlt covers a total
of eight rows and is adjustillble in increments of one row
{R1. R2, R4l. The horizonUI plane adjustment increments
by two charac'lers for a totilll coverage of 16 character posi-
tions. Both adjustments lire ac<;omplished with the use of
wired "AND" gates U22 and U38 {LS266J.
PROCESSOR
The CPU chip is a Z.sO that runs at a clock speed of 2.02752
MHz. The CPU clock is derived by dividing the basic video
clock (10.1376 MHz) by five. U62 performs this function
and the dock is
non~ymmetrical
with a 40 percent high duty
cycle. The dock signal POC is run through
an
active pull-up
and becomes PCLOCK which has a
full 5''1011
swing with fan
rise and fall times. The reset switch. which is located on the
keyboard. is ORed with power on reset (R7. C54. U15) to
provide a System RESET"' signal. The Reset pin on the
Z.g()
is driven by RESET". The MIdress lines are buffered by
LS244's (U91, U92), the data lines by an LS245 (USO). and
control lines buffered by an lS367 (U76). The buffered
control lines are combined in Ua9 and US6 to form memory
and 10 port controls (RD·, WR·. IN·, OUT·).
See
the CPU Timing Diagram for exact time relationships.
U75 is used to
S>N
tch the data bus buffer during INT AK·
cycle or any read operation (10 01 Memory). Whenever one
of the ROM's IS being acceued, the data bus buffer is dis·
abled by U108 since Ihe ROM's dala lines are located on the
CPU dala bus, BUSRO', HALT", BUSAK". and RFSH' are
not used. The Model III has three sockets for the ROMs
U104, Ul05, U106). They are 64K bit,32K t>it and 16K bil
ROMs, reslJectillcly.
AAM
The RAM consists of an array of up to twenly-four 16K
dynamic memory chips with damping resinors located on all
address and control lines (RP1, RP2. RP3). Chips U710 U14
are addressed at 4000 to 7FFF. U25 to U32 are addressed at
8000 to BFFF and U43 to U50 are addressed at Cooo 10
FFFF. The memory data is interfaced to the data bus by
1\'\/0 8T26s (U63, U64). Normally the data is driven Into the
memory array. However. on a read cycle U19 switd1es the
direction of the transceivers and drives memory dala onto
the data bus. The· 5 volts required by the RAMs is supplied
by a 3·terminal regulator (MC7905Cl which takes -12 volts
as its input. See the CPU Timing Diagram for the relationship
between RAS". MUX, CAS·,
_
.
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FIGURE 1. CPU TIMING DIAGRAM
13