Radio Shack TRS-80 Service Manual page 24

If V07 is a one and V06 is a zero, 1hen a graphics
char·
acter will be displayed which uses LS153 (U54j .nd
LS244 IU531 to load the data into the shift register. Note
that both U36 and U53 are tri -state devices and that the
enables for thesedevices(OL YCHAR" and DLYG RAPH·
IC') are the complements of each other. This means th<lt
either character data or grephics data will be loaded into
the shift register depending of course on the state of VD7
and VD6. The signal ENALTSET and <In LSOO (U37)
allow the
64
characters that are m<lsked by the graphics
characters to
be
displayed from the ROM (U36). When
ENALTSET is a one. the 64 standard characters are dis·
played. When ENALTSET is
II
zero, 64 alternate char·
acters are displayed.
O. The wait logic forces the CPU into a wait >tate if the
BLANK' signal is not present. This allows video RAM
updates only during horizontal retrace. vertical retrace.
and the blanking on the last four scan lines of a character
since these are the oonditions that form BLANK-. This
will eliminate virtually all the "hashing" on the display.
The logic consists of U17. U16, U18. U57, U39. and Ul.
When VID' is true, indicating the CPU wants access
to
the video RAM, and PBLANK' is false, both signals are
oombined in U16 to give PWAIT'. If PBLANK' istrue,
it is combined with VIO" to give RSVID' ,which is then
granted access to the video AAM. This feature can be
disabled through the OISWAIT input to U39 which is
under software control.
KEYBOARD
The keyboard interface consists of open collector drivers
(LOO51 U34 and U35 which feed the B by B key matrix with
addresses AO through A7. The Ou1,)ut of the matrix has the
pullup resistors and CMOS receivers which give reliable key
closure sensing even with key switches of up to 300 ohm
resistance. The data from the CMOS huffer is driven onto the
data bus by the LS240 (USS). The signal KYBD' strobes the
octal data bus driver. The reset switch is also mounted on the
keyboard assembly and the three lines required are routed in
the twenty·pin keyboard cable to the reset circuit. Note that
all electronic parts are mounted on the CPU Board; none are
required on the PCB for the keyboard.
CASSETTE INTERFACE
There are two sep¥ate casselle circuits lor 500 Baud and
1500 Baud. The 500 Baud Read circuitry is very similiar in
j)l'"inciple to the Read circuitry on Model I. The MC1741
forms a two pole high P35S active filter to filler out 60 Hi
noise. The two amplifiers 01 the MCI458 (U80) form
it
full-
wave active rectifier. Capacitor C94 acu to smooth out the
rectified output which is then led to
l)
339 comparator lU96I.
Resistors R48. A49, and ASl provide a fixed threshold of
O.5V at pin 5 of U96. This gives a minimum level with which
the irIput signal at pin 4 may be compared against. Capacitor
C93 provides a voltage equal to the average signal level, with
R46 and CA9 providing fast charge and R48 providing a slow
dischuge. Capacitor C93 provides an equivalent AGC action
since the comparator threshold becomes proportional to the
signal level. The comparator outputs negative pulses cor-
responding to the input pulses which are then inverted by
U2 and fed into the clock of
a "0" flip-flop (U3). The "0"
flip-flop will then be set and will stay set until cleared by
CAS OUT· (equivalent to OUTSIG in Model
II.
CAS
IN'
will read the data stored in U3 and output it at pin 7 of the
data bus.
The
500
Baud Write circuitry is identical to the write cir-
cuitry used in the Model I. This circuit is also used to provide
the squarewave datil for 1500 BaUd. Data DOH gives O.4V
out, Data 01 H gives 0.8V out, and Data 02H gives O.OV
OUI.
The 1500 Baud uses 0' Hand 02H only. The 500 Baud out·
put is
a
250l1sec pulse white the 15Q() Baud output is a
squarewave that varies in frequency between 1320 Hz and
2680 Hz.
The 1500 Baud cassette input consists 01 a zero crossing
detector using U9S. Diode CRB is used to prevent the input
signal from driving pin 1001 U96 negative. The output. pin
13 of U96, is normally high when the signal is applied and
will provide a 50mV threshold at pin 11. A57 and R59 pro·
vide this SOmV of threshold and hysteresis. The output of
the comp¥ator is fed to the two 74LS74 "0" flip-flops
which determine whether the rising or falling edge is detected
and is also used to set an interrvpt signal INT· using U18 and
U35. ENCASINTF, pin 2, enables
the
falling edge inte"upt
latch and ENCASINTR, pin 12, enables the rising edge inter·
rupt latch. Only one of the latches are enabled at anyone
time. CASIN· clears the interrupt latches and RDINT·
STATUS· is used to read thedau from the interrupt latch to
tell which latch has been set. The cassette motor on relay is
driven by U97.
17