Line Status Register - IBM 5150 Hardware Reference Manual

Table 23. BAUD RATE AT 1.843 Mhz
Desired
Divisor Used
Percent Error
Baud
to Generate
Difference Between
Rate
16x Clock
Desired & Actual
Decimal Hex
50
2304 '900' -­
75 1536 '600' - ­
110 1047
'417'
0.026
134.5
857
'359'
0.058
150
768 '300' -­
300 384
'180' -­
600 192 'OCO' -­
1200 96
'060'
- ­
1800
64 '040'
- ­
2000
58 '03A'
0.69
2400 48 '030'
- ­
3600
32 '020'
- ­
4800
24 '018'
-­
7200
16 '010'
- ­
9600
12 'OOC' -­
~
Line Status Register
This 8-bit register provides status information to the CPU concerning
the data transfer. The contents ofthe Line Status Register are indicated
and described below.
Line Status Register (LSR)
3FD
BIT
6
4 3
2 1
0
DATA READY (DR)
OVERRUN ERROR (OR)
I
Li=:
PARITY ERROR (PE)
...
FRAMING ERROR (FE)
!:
BREAK INTERRUPT (BI)
:.
.
TRANSMITTER HOLDING
REGISTER EMPTY (TH RE)
...
po
TX SHIFT REGISTER
EMPTY (TSRE)
=0
-
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