IBM 5150 Hardware Reference Manual page 267

LOC OBJ
LINE SOURCE
H20 C3
5415 RET ;WE ARE FINISHED
5416
WRITE_BYTE ENDP
5417
1----- --- - -- --- -- -------------------- --- ­
FAZE
5418 WRITE_BIT
PROC NEAR
5419
; PURPOSE:
5420
5421 TO WRITE A oAT A BI T TO CASSETTE
5422 CARRY FLAG CONTAINS DATA BIT
5423
I.
E. IF SET DATA BIT IS A ONE
5424 IF ClEAR DATA BIT IS A ZERO
5425
5426 NOTE: TWO EDGES ARE WRITTEN PER BIT
5427
ONE BIT HAS 500 USEe BETWEEN EDGES
5428
FOR A 1000 USEC PERIOD (1 MllLISEC)
5429
5430 ZERO BIT HAS 250 USEC BETWEEN EDGES
5431
fOR A. SOD USEC PERIOD (.5 MIlLISEC)
5432
; CARRY FLAG IS DATA BIT
5433
1---- -------------------------------------- ­
5434
;ASSUME IT'S A
','
FAZE 88,6.004 5435 MOY AX.1l84 ; SET AX TO NOMINAL ONE SIZE
FA31 7203 5436
JC
; JUMP IF ONE BIT
w,.
FA33 885002 5437 MOY AX,59Z ; NO, SET TO NOMINAL ZERO SIZE
FA36 5438 10126:
; WRITE-BIT-AX
FA36 50
5439 PUSH AX
iWRITE BIT WITH PERIOD EQ TO VALUE AX
FA37 5440
10129:
FA37 E462
5441 IN AL,PORT_C
; INPUT TIMER_O OUTPUT
FH9 2420 5442 AND AL,020H
FA38 74F,6. 5443
Jl
WZ9
,lOOP TIll HIGH
FA30 5444
10130:
FA30 E462 5445 IN Al.PORT_C
;NOW WAIT TILL TIMER'S OUTPUT IS LOW
F,6.3F 2420 5446
AND
AL,020H
FA41 75FA 5447 JHZ W3.
5448
jRElOAD TIMER WITH PERIOD
5449 iFOR NEXT DATA BIT
. .
FA43 58 5450 POP ;RESTQRE PERIOD COUNT
FA44 5451
10131: SET TIMER
FA44 E642
5452
,
OUT
"
0 42H, AL ; SET LOW BYTE OF TIMER
2:
FA46 BAC4 5453 MOV
AL, AH
FA48 E642 5454
OUT
042H. AL
; SET HIGH BHE OF TIME~ 2
FA4A C3
5455
RET
545~ WRITE_BIT ENDP
""Ii'
"
~;~=~;~---------;;~~----~;~;-------
------ ­
FA48
, 5458
.. 5459
UPDATE CRC REGISTER WITH NEXT DATA BIT
,
,
5460
..
5461 CRe IS USED TO DETECT READ ERRORS
:\
5462 •
."
,
5463
ASSUMES DATA BIT IS IN CARRY
REG AX IS MODIFIED
FLAGS ARE MODIFIED
5467
F,6.48 ,6.16900 5468 MOY
5469 j
THE FOLLOWING INSTUCTIONS
5470
JWILL SET THE OVERFLOW FLAG
5471
j
IF
~ARRY
AND MS BIT OF CRe
5472
JARE UNEQUAL
FA4E 0108
5473 RCR AX.1
FA50 0100 5474 RCL
AX,I
1A52 F8
5475 eLe
;CLEAR CARRY
FA53 7104
5476
JNO
,SKIP IF NO OVERflOW
5477
;IF DATA BIT XORED WITH
5478
; CRe REG BIT 15 IS ONE
FA55 351008 5479 xtJR
AX.D810H ; THEN XOR CRC REG WITH
5480 ; oa10H
FA58 F9
5461
STC
;SET CARRY
F,6.59 5482 10132:
W"
AX.,
FA59 0100 5483 RCL
iROTATE CARRY (DATA BIT)
5484
jlNTO CRe REG
FA5B ,6.36900 5485
Mev
CRC_REG.AX
;UPDATE CRC_REG
FASE C3 5486
RET
; FINISHED
5487
CRe_GEN
ENDP
5488
;------------------------------------------- ­
F,6.5F 5469 PROC NEAR
; START TAPE AtJO DELAY
5490
5491
;
------------------------------------------- ­
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