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Contec PC-686(CPCI)-LV User Manual

Compactpci single board computer for socket 370 cpu (celeron, pentium iii) with lan/vga
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PC-686(CPCI)-LV
CompactPCI Single Board Computer
For socket 370 CPU (Celeron™, Pentium III™)
With LAN/VGA
User's Manual

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Summary of Contents for Contec PC-686(CPCI)-LV

  • Page 1 PC-686(CPCI)-LV CompactPCI Single Board Computer For socket 370 CPU (Celeron™, Pentium III™) With LAN/VGA User’s Manual...
  • Page 3 CONTEC Co., Ltd. CONTEC Co., Ltd. makes no commitment to update or keep current the information contained in this document. The information in this document is subject to change without notice.
  • Page 4 Limited One Year Warranty CONTEC Industrial CPU board is warranted by CONTEC Co., Ltd. to be free from defects in material and workmanship for up to one year from the date of purchase by the original purchaser. Repair will be free of charge only when this device is returned freight...

  • Page 5: Table Of Contents

    Table of Contents Table of Contents ................. 1 HAPTER NTRODUCTION Specification..................1 Mechanical & Environmental ............... 2 Check List ..................... 3 Description .................... 4 Power Management Features ..............7 Power Requirements................9 Connector & Jumper Location ............10 Block Diagram ..................11 .............
  • Page 6 Table of Contents 2.17 CompactPCI connector P3: CN14 ............34 2.18 Reset button: S1 ...................34 2.19 LED Indicator ..................34 ..............35 HAPTER UMPER ETTING Infrared (IrDA) port: JP1..............35 Watchdog Timer output selector: JP2 ...........35 CN16 RS-232C/RS-422/RS-485 Selector: JP3/JP5 .......36 RS-422/RS-485 Terminator: JP4 ............39 On board LAN selector: JP6..............39 DISK ON CHIP Memory Add.
  • Page 7 Table of Contents 5.6. Hardware Monitor................56 BIOS S ................. 65 HAPTER ETUP 6.1. Introduction ..................65 6.2. Main Menu..................68 6.3. Standard CMOS Setup................. 70 6.4. BIOS Features Setup................72 6.5. Chipset Features Setup ................ 76 6.6. Power Management Setup ..............80 6.7.
  • Page 8 Table of Contents PC-686 (CPCI)-LV User’s Manual...

  • Page 9: Chapter 1 Introduction

    CHAPTER 1 – Introduction Chapter 1 Introduction Specification Processor Socket: Socket 370 ® Processor: Intel Celeron™ 300MHz – 566MHz; Pentium III™ (FSB:100MHz) 500MHz – 700MHz Host Bus: CompactPCI Bus for PICMG2.0 R2.1 Bus Master is supported till 4 Max. ® Chipset: Intel 440BX Cache Size: 128KB L2 cache is integrated in the Celeron™...

  • Page 10: Mechanical & Environmental

    CHAPTER 1 – Introduction Hardware Monitor: Winbond W83781D IrDA: One 1x6 Pin-header Keyboard connector: PS/2 keyboard connector Mouse connector: PS/2 Mouse connector VGA Connector: C&T 69000 Controller, 15 pin D-type VGA Connector LCD: C&T 69000 Controller, 41pin VESA Connector (for OEM) LAN: Intel 82559 LAN controller, RJ-45 connector SSD: DIP socket supports DiskOnChip flash disks (2MB~144MB) RTC: battery backup by Lithium Battery (CR2032)

  • Page 11: Check List

    CHAPTER 1 – Introduction BOARD DIMENSION: 160mm(L) x 233.35mm(H) / 6.23inch x 9.19inch. BOARD WEIGHT: 500g Check List Please check that your package is complete and contains the items below. If you discover damaged or missing items, please contact your dealer. The PC-686(CPCI) Industrial CPU Board This User’s Manual &...

  • Page 12: Description

    CHAPTER 1 – Introduction Description The PC-686(CPCI) is a CompactPCI standard Industrial CPU board based on Intel’s 440BX chipset and is fully designed for harsh industrial environment. It features socket 370 compatible with Intel’s processor. This board accommodates up to 768MB of SDRAM memory. The PC-686(CPCI) comes with onboard CPU temperature sensor to protect your processor from overheating (Winbond W83977HF chipset).
  • Page 13 CHAPTER 1 – Introduction Graphics Acceleration 64-bit Single Cycle BitBLT engine System/Screen-Screen BitBLT 256 3-op Raster Operations Color Expansion Instant Full Screen Page Flip Simultaneous Hardware Cursor and Pop-up Window 64x64 pixels by 4 colors 128x128 pixels by 2 colors Standards Supported Fully IBM®...
  • Page 14 CHAPTER 1 – Introduction Integrated Clock Synthesizers 135 MHz RAMDAC 83 MHz Memory Clock with PLL Advanced On-chip Power Management Standby mode Panel-off power saving mode Zero volt suspend Eight GPIO pins Activity Detection Output Pin C&T 69000 Graphic Accelerator Refresh Rates Resolution Color 60(Hz)

  • Page 15: Power Management Features

    CHAPTER 1 – Introduction Power Management Features 1.5.1. Overview The PIIX4 power management function provides a wide range of capabilities and configuration options allowing a system designer to implement a wide range of power saving modes. PIIX4 provides for four main areas of power management: Clock Control and Processor Complex Management Peripheral Device Management System Management (SMI Generation, System Management Bus)
  • Page 16 CHAPTER 1 – Introduction Power-on-Suspend (POS) with three system reset options Suspend-to-RAM (STR) Suspend-to-Disk (STD) or Soft OFF (SOff) Global Standby Timer (also active during suspend) to monitor for overall system idleness and as a resume timer Power Button Input Override feature forcing immediate transition to Soft Off Battery Low indication pin Shadow registers for standard AT write only registers to save and restore system...

  • Page 17: Power Requirements

    CHAPTER 1 – Introduction Power Requirements Your system requires a clean, steady power source for reliable performance of the high frequency CPU on the PC-686(CPCI) Industrial CPU board, the quality of the power supply is even more important. For the best performance make sure your power supply provides a range of the following table DC power source.

  • Page 18: Connector & Jumper Location

    CHAPTER 1 – Introduction Connector & Jumper Location PC-686 (CPCI)-LV User’s Manual...

  • Page 19: Block Diagram

    CHAPTER 1 – Introduction Block Diagram SOCKET 370 CLK GEN. GTL+ BUS 443BX DIMM X 3 TERMINATOR PCI BUS USB #1, #2 PIIX4E (82371EB) (82559ER) (69000) IDE#1, #2 ISA BUS COM #1, #2 BIOS MONITOR SUPER I/O (W83977TF) KB / MS PC-686 (CPCI)-LV User’s Manual...
  • Page 20 CHAPTER 1 – Introduction PC-686 (CPCI)-LV User’s Manual...

  • Page 21: Chapter 2 Hardware Installations

    CHAPTER 2 –Hardware Installations Chapter 2 Hardware Installations This chapter provides information on how to use the jumpers and connectors on the PC-686(CPCI) in order to set up a workable system. Installation procedure 2.1.1 Install the processor with correct orientation. 2.1.2 Insert the DRAM module with correct orientation.

  • Page 22: Cpu Installation

    CHAPTER 2 –Hardware Installations CPU Installation: ® The PC-686(CPCI) Industrial CPU Board supports Intel Celeron Pentium III processor. The processor’s VID pins automatically program the Core voltage regulator on the CPU board to the required processor voltage. The host bus speed is automatically selected. The processor connects to the CPU board through the 370-pins ZIF PPGA socket.

  • Page 23: Main Memory Installation: Dimm1, Dimm2, Dimm3

    CHAPTER 2 –Hardware Installations Main Memory Installation: DIMM1, DIMM2, DIMM3 The PC-686(CPCI) Industrial CPU Board supports three dual inline memory module (DIMM 168-pin) sockets for a maximum total memory of 768MB. Using the serial presence detect (SPD) data structure, programmed into an E PROM on the DIMM, the BIOS can determine the SDRAM’s size and speed.
  • Page 24 CHAPTER 2 –Hardware Installations DIMM size Non-ECC configuration ECC configuration 64MB 8Mbit x 64 8Mbit x 72 128MB 16Mbit x 64 16Mbit x 72 256MB 32Mbit x 64 32Mbit x 72 Note: All memory components and DIMMs used with the PC-686(CPCI) CPU board must comply with the PC SDRAM Specification.
  • Page 25 CHAPTER 2 –Hardware Installations 100-MHz SDRAM DIMM serial presence detect via SMBus interface 16 and 64-Mbit devices with 2K, 4K and 8K page sizes x4, x8, x16, and x32 DRAM widths SDRAM 64-bit data interface with ECC support Symmetrical and asymmetrical DRAM addressing A.G.P.
  • Page 26 CHAPTER 2 –Hardware Installations buffers A.G.P. dedicated inbound/outbound FIFOs (133/66 MHz), used for temporary data storage Power management functions Support for system suspend/resume (DRAM and power-on suspend) Compliant with ACPI power management SMBus support for desktop management functions Support for system management mode (SMM) Intel 82371EB PCI ISA IDE Xcelerator (PIIX4E) The PIIX4E is a multifunction PCI device implementing the PCI-to-ISA bridge, PCI IDE functionality, USB host/hub functionality, and enhanced power...
  • Page 27 CHAPTER 2 –Hardware Installations 33MB/sec Bus master mode with an 8 x 32-bit buffer for bus master PCI IDE burst transfer Enhanced DMA controller Two 8237-based DMA controllers Support for PCI DMA with three PC/PCI channels and distributed DMA protocols Interrupt controller based on 82C59 Support for 15 interrupts Programmable for edge/level sensitivity...

  • Page 28: Lan Connector: Cn1

    CHAPTER 2 –Hardware Installations Demultiplexing of address and data on the bus for near 100 percent bus efficiency AC timing for 133MHz data transfer rates, allowing real data throughput in excess of 500 MB/sec RJ-45 LAN connector: CN1 ® The PC-686(CPCI) CPU board is used Intel 82559 PCI LAN chipset for LAN controller, the controller’s features include: CSMA/CD Protocol Engine...

  • Page 29: Serial Port Connector: Cn2

    CHAPTER 2 –Hardware Installations The follow table shows the pin assignments of this connector. The category-5 cable is required for transmission at 100Mbps. PIN No. Function C N 1 N.C. N.C. N.C. N.C. Serial Port connector: CN2 COM1 and COM2 is a connector that with two 9 pin D-type header, is onboard serial ports of the CPU board PC-686(CPCI).
  • Page 30 CHAPTER 2 –Hardware Installations 2.5.1. RS-422/RS-485 specifications Transmission system: Asynchronous, half-/full-duplex serial transmission conforming to RS-422/RS-485 Baud rate: 19200 to 50bpx (programmable) Signal extensible distance: 1.2km Max. Note: The mouse and keyboard can be plugged into either PS/2 connector. Power to should be turned off before a keyboard or mouse is connected or disconnected.

  • Page 31: Parallel Port Connector: Cn3

    CHAPTER 2 –Hardware Installations Parallel Port Connector: CN3 The parallel port bracket can used to add an additional parallel port for additional parallel devices. There are four options for parallel port operation: Compatible (Standard mode) Bi-Directional (PS/2 compatible) Bi-Directional EPP. A driver from the peripheral manufacturer is required for operation.

  • Page 32: Ps/2 Mouse & Keyboard Stack Connector: Cn4

    CHAPTER 2 –Hardware Installations PS/2 Mouse & Keyboard stack Connector: CN4 ® The CPU board provides a standard PS/2 mouse mini DIN connector for ® ® attaching a PS/2 mouse. You can plug a PS/2 mouse directly into this connector. The Connector pin definition is shown below: PIN No.
  • Page 33 CHAPTER 2 –Hardware Installations The CPU board has two USB ports; one USB peripheral can be connected to each port. For more than two USB devices, an external hub can be connected to either port. The two USB ports are implemented with stacked back panel connectors.

  • Page 34: Vga Connector: Cn6

    CHAPTER 2 –Hardware Installations VGA Connector: CN6 It is a VGA CRT connector (HD-SUB15[Female]). The pin assignments are as follows: PIN No. Function PIN No. Function N.C. GREEN BLUE D-DATE N.C. N.C. H-SYNC V-SYNC D-DCLK PC-686 (CPCI)-LV User’s Manual...

  • Page 35: Lcd Connector: Cn7

    2.10 LCD Connector: CN7 CN7 is a 41-pin connector for flat panel LCD displays. The following shows the pin assignments of this connector.(HIROSE DF9A-41P-1V) When you use the LCD display series(CONTEC products), you need the LCD exchange display board (for OEM). PIN No.

  • Page 36: Cpu Fan Connector: Cn8

    CHAPTER 2 –Hardware Installations 2.11 CPU FAN Connector: CN8 CN8 is a 3-pins box-header for the CPU cooling fan power connector. The fan must be a 12V fan. Pin 3 is for Fan speed sensor input. Housing:5102-03(Molex) PIN No. Function Contact:5103(Molex) DC+12V FAN_Sensor...

  • Page 37: Floppy Disk Connector: Cn9

    CHAPTER 2 –Hardware Installations 2.12 Floppy Disk Connector: CN9 In the Setup program, the floppy interface can be configured for the following floppy drive capacities and sizes: 360 KB, 5.25-inch 1.2 MB, 5.25-inch 720 KB, 3.5-inch 1.2 MB, 3.5-inch 1.25/1.44 MB, 3.5-inch 2.88 MB, 3.5-inch This connector supports the provided floppy drive ribbon cable.

  • Page 38: External Battery Connector: Cn10

    CHAPTER 2 –Hardware Installations 2.13 External Battery Connector: CN10 It is a 2 Pin connector used for external battery. An external battery powers the real-time clock and CMOS memory. PIN No. Function Housing:XHP-2(JST) CN10 Contact:SXH-001T-P0.6(JST) Ext_bat Note: In using the external battery, you need 1-2pin short of JP11. And the available external battery is Lithium battery that the Voltage is 3V.
  • Page 39 CHAPTER 2 –Hardware Installations LS-120 drive as a bootable device in both 120 MB and 1.44MB mode. Connection of an LS-120 drive and a standard 3.5-inch diskette drive is allowed. The LS-120 drive can be configured as a boot device if selected as Drive A in the BIOS setup program.

  • Page 40: Compactpci Connector P2: Cn12

    CHAPTER 2 –Hardware Installations 2.15 CompactPCI connector P2: CN12 Pin No. CLK1 REQ1# GNT1# REQ2# CLK2 CLK3 SYSEN# GNT2# REQ3# CLK4 GNT3# REQ4# GNT4# CN12 BRSVP2B4 C-BE7# C/BE6# C/BE5# C/BE4# PAR64 AD63 AD62 AD61 AD60 AD59 AD58 AD57 AD56 AD55 AD54 AD53 AD52...

  • Page 41: Compactpci Connector P1: Cn13

    CHAPTER 2 –Hardware Installations 2.16 CompactPCI connector P1: CN13 Pin No. - 12V TRST# +12V CN13 INTA# INTB# INTC# INTD# BRSVP1A INTP INTS BRSVP1A BRSVP1B RST# GNT# REQ# 3.3V AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 3.3V...

  • Page 42: Compactpci Connector P3: Cn14

    CHAPTER 2 –Hardware Installations 2.17 CompactPCI connector P3: CN14 This Connector is to IDE Connector Signal and Floppy connected Disk Connector Signal. Pin No. CN14 DSKCHG# HEAD# WRATA# WPRT# N.C. TRAK0# WGATE# WDATA# STEP# N.C. Floopy Signals FDIR# MOTB# DSA# DSB# N.C.

  • Page 43: Chapter 3 Jumper Setting

    CHAPTER 3 – Jumper Setting Chapter 3 Jumper Setting Infrared (IrDA) port: JP1 Serial Port 2 can be configured to support an IrDA module connected to this 6-pin header. After the IrDA interface is configured, files can be transferred to or from portable devices such as laptops, PDAs and printers using application software.

  • Page 44: Cn16 Rs-232C/Rs-422/Rs-485 Selector: Jp3/Jp5

    CHAPTER 3 – Jumper Setting CN16 RS-232C/RS-422/RS-485 Selector: JP3/JP5 8 10 12 14 16 18 20 22 24 RS-232C 11 13 15 17 19 21 (Default) 8 10 12 14 16 18 20 22 24 11 13 15 17 19 21 RS-422 8 10 12 14 16 18 20 22 24...
  • Page 45 CHAPTER 3 – Jumper Setting 3.3.1. Transmit date control in half-duplex mode In half-duplex mode, the transmission buffer must be controlled to prevent transmit data from causing a collision. The PC-686(CPCI) uses the RTS signal and bit 1 in the modem control register to control transmit data. Modem control register (Setting I/O address +4H) bit 1: 0 …...
  • Page 46 CHAPTER 3 – Jumper Setting RS-485 Setting 3.3.3. I/O addresses and instructions The table below lists I/O addresses for use as COM2. I/O address DLAB Read/Write Register Transmitter holding Register Receiver buffer Register 02F8H Divisor latch Register (LSB) Divisor latch Register (MSB) 02F9H Interrupt enable Register 02FAH...

  • Page 47: Rs-422/Rs-485 Terminator: Jp4

    CHAPTER 3 – Jumper Setting RS-422/RS-485 Terminator: JP4 Terminator Function No terminating resister (Default) CTS for RS-422 terminating resister provided RTS for RS-422 terminating resister provided RXD for RS-422/RS-485 terminating resister provided TXD for RS-422/RS-485 terminating resister provided On board LAN selector: JP6 Function Disabled Enabled (Default)

  • Page 48: Disk On Chip Memory Add. Selector: Jp7

    CHAPTER 3 – Jumper Setting DISK ON CHIP Memory Add. Selector: JP7 You can select the memory address by JP7 setting, after equip DiskOnChip with the SSD Socket. Below are 4 kinds of DiskOnChip memory address configuration. Function J P 7 0DC00~ 0DDFFh J P 7 0D800h~0D9FFh...

  • Page 49: Clear Cmos Content: Jp10

    CHAPTER 3 – Jumper Setting Clear CMOS Content: JP10 The time, date, and CMOS values can be specified in the Setup program. The CMOS values can be returned to their defaults by using the Setup program. The RAM data contains the password information is powered by the onboard button cell battery.
  • Page 50 CHAPTER 3 – Jumper Setting PC-686 (CPCI)-LV User’s Manual...

  • Page 51: Chapter 4 Cpu Board Resources

    CHAPTER 4 – CPU Board Resources Chapter 4 CPU Board Resources 4.1. I/O MAP Address (hex) Size Description 0000 ~ 000F 16 bytes DMA Controller 0020 ~ 0021 2 bytes Interrupt Control (PIC) 002E ~ 002F 2 bytes Super I/O controller configuration registers 0040 ~ 0043 4 bytes System timer 1...

  • Page 52: Memory Map

    CHAPTER 4 –CPU Board Resources Address (hex) Size Description 03B0 ~ 03BB 12 bytes Video (Monochrome) 03C0 ~ 03DF 32 bytes Video (VGA) 03E8 ~ 03EF 8 bytes COM3 03F0 ~ 03F5, 03F7 8 bytes Diskette controller 03F6 1 byte Primary IDE channel 03F8 ~ 03FF 8 bytes...

  • Page 53: Dma Channels

    CHAPTER 4 – CPU Board Resources 4.3. DMA Channels Data Width System Resources 8 or 16bits Reserved 8 or 16bits Reserved(or parallel port (for ECP)) 8 or 16bits Diskette drive 8 or 16bits Reserved(or parallel port (for ECP)) Reserved – cascade channel 16bits Open 16bits...

  • Page 54: Interrupters

    CHAPTER 4 –CPU Board Resources 4.5. Interrupters IRQ # System Resources I/O Channel check Reserved, interval timer Reserved, keyboard controller Reserved, cascade interrupt from slave PIC COM2* COM1* LPT2 (Plug and Play option)/audio/user available Diskette drive controller LPT1* Real time clock ACPI USB/User available User available...

  • Page 55: Pci Interrupters Routing Map

    CHAPTER 4 – CPU Board Resources 4.6. PCI Interrupters Routing Map This section describes interrupt sharing and how the interrupt signals are connected between the PCI expansion slots and onboard PCI devices. The PCI specification specifies how interrupts can be shared between devices attached to the PCI bus.
  • Page 56 CHAPTER 4 –CPU Board Resources PCI Interrupt Routing Map PIIX4E Power A. G. P. PIRQ Manage Slot Slot Slot Slot Audio Slot Signal ment PIRQA INTA INTD INTC INTB INTA INTA PIRQB INTB INTA INTD INTC INTB PIRQC INTC INTB INTA INTD INTA...

  • Page 57: Chapter 5 Software Utilities

    CHAPTER 5 – Software Utilities Chapter 5 Software Utilities This chapter introduces the software utilities supplied for PC-686(CPCI) ® which including a 10/100M Ethernet driver, Intel 440BX chipset Core PCI&ISAPNP services / Graphics drivers for CRT/Flat Panel Driver and watchdog function configuration utility.

  • Page 58: Graphic Driver

    CHAPTER 5 – Software Utilities 5.2. Graphic Driver 5.2.1. Introduction The CPU board PC-686(CPCI) is adopted the Chips 69000 for PCI board VGA / LCD designs. The 69000 integrate high performance memory technology for the graphics frame buffer. Based on the proven HiQVideo™ graphics accelerator core, the 69000 combines state-of-the-art flat panel controller capabilities with low power, high performance integrated memory.
  • Page 59 CHAPTER 5 – Software Utilities Versatile Panel Support The 69000 supports a wide variety of monochrome and color Single-panel, Single-Drive (SS) and Dual-Panel, Dual Drive (DD), standard and high-resolution, passive STN and active matrix TFT/MIM LCD, and EL panels. With HiQColor technology, up to 256 gray scales are supported on passive STN LCDs.
  • Page 60 CHAPTER 5 – Software Utilities output). This is important for the 69000 since the video must be stored in the integrated 2MB frame buffer and thus optimized to require very little space. Storing data in the native YUV format uses less memory for video while providing excellent playback display quality.

  • Page 61: Lan Driver

    CHAPTER 5 – Software Utilities This driver allows Chips 69000 to support Windows NT 4.0.: ; Windows NT 3.51 Windows 98 This driver allows Chips 69000 to support Windows 98 platform: . Windows 3.1 This driver allows CHIPS 69000 to support Windows 3.1: Windows 2000 About Windows 2000, please use the standard VGA Drivers in the OS.

  • Page 62: Watchdog-Timer (Wdt) Setting

    CHAPTER 5 – Software Utilities 5.4. Watchdog-Timer (WDT) Setting WDT is widely used for industry application to monitoring the activity of CPU. Application software depends on its requirement to trigger WDT with adequate timer setting. Before WDT time out, the functional normal system will reload the WDT.

  • Page 63: Update New Version Bios

    CHAPTER 5 – Software Utilities 5.5. Update new version BIOS Steps 1: Make a record of your original or existing BIOS Setup parameters. Press [Del] during the Power-On-Self-Test to enter BIOS Setup Program and write down the value of each parameter in order to re-configure your System after BIOS updating Step 2: Make a System Disk.

  • Page 64: Hardware Monitor

    CHAPTER 5 – Software Utilities 5.6. Hardware Monitor Hardware Monitor function is included in Hardware Monitor controller (Winbond W83781D) on PC-686(CPCI)-LV. You can read Temperature, Voltage and Fan Sensor output of SBC. 5.6.1. Temperature Two Thermistors are mounted on SBC as following. You can read Temperature of this position.
  • Page 65 CHAPTER 5 – Software Utilities 5.6.4. W83781D Registers There are two ports to read W83781D Hardware Monitor Registers. These two ports are described as following. Index Register : 295h Data Register : 296h The registers Index is showed as next page. <Sample Program: Read Chip ID Register to bx>...
  • Page 66 CHAPTER 5 – Software Utilities Chip ID Register <10h> 59h-5Fh Reserved BANK1 50h-51h Sensor 2 Temperature reading 52h-5Fh Sensor2 Temperature Configuration Register (*1) BANK2 50h-5Fh Sensor3 Temperature Register (not in use) BANK3 50h-5Fh Reserved BANK4 50h-5Fh Reserved BANK5 50h-5Fh Reserved BANK6 50h-5Fh Reserved...
  • Page 67 CHAPTER 5 – Software Utilities Vcore reading Register(20h) VTT(V) = 16mV x ReadData VTT(1.5V) reading Register(21h) Vcore(V) = 16mV x ReadData +3.3V reading Register(22h) V3.3(V) = 16mV x ReadData +5V reading Register(23h) V5(V) = 16mV x ReadData x 1.68 +12V reading Register(24h) V+12(V) = 16mV x ReadData x 3.8 -12V reading Register(25h) V-12(V) = (16mV x ReadData)- (3.48)
  • Page 68 CHAPTER 5 – Software Utilities CN8 FAN sensor Reading Register(28h) RPM = 1.35x10 / ( ReadData x FAN_sensor1_Divisor) VID/FAN Register (47h) VID0 VID1 VID2 VID3 FAN_Sensor1_Divisor_B0 FAN_Sensor1_Divisor_B1 FAN_Sensor2_Divisor_B0(not in use) FAN_Sensor2_Divisor_B1(not in use) Bit 7-6:FAN_Sensor2 Divisor Bit 1-0(not in use) Bit 5-4:FAN_Sensor1 Divisor Bit 1-0 Bit 3-0:VID<3:0>...
  • Page 69 CHAPTER 5 – Software Utilities FAN Divisor Table: Bit1 Bit0 Divisor VID(Vcore) Table: Processor Pins Processor Pins 0=Connected to Vss Vcore 0=Connected to Vss Vcore 1=Open or Pull-UP to Vin 1=Open or Pull-UP to Vin VID4 VID3 VID2 VID1 VID0 VDC VID4 VID3 VID2 VID1 VID0 VDC 2.05 2.00...
  • Page 70 CHAPTER 5 – Software Utilities Chip ID Register(BANK0:58h) CHIPID Bit 7-0:Winbond Chip ID number. Read this register return “11h”. Temperature Sensor2 Temperature Register1(BANK1:50h) TEMP2 <8:1> Please refer to temperature Sensor2 Data Format Table PC-686 (CPCI)-LV User’s Manual...
  • Page 71 CHAPTER 5 – Software Utilities Temperature Sensor2 Temperature Register2(BANK1:51h) Reserved Reserved Reserved Reserved Reserved Reserved Reserved TEMP<0> Please refer to temperature Sensor2 Data Format Table Temperature Sensor2 Data Format Table: Temperature TEMP<8:1> TEMP<0> +125 +0.5 -0.5 PC-686 (CPCI)-LV User’s Manual...
  • Page 72 CHAPTER 5 – Software Utilities PC-686 (CPCI)-LV User’s Manual...

  • Page 73: Chapter 6 Bios Setup

    CHAPTER 6 - BIOS SETUP Chapter 6 BIOS Setup 6.1. Introduction This chapter discusses Award’s Setup program built into the FLASH ROM BIOS. The Setup program allows users to modify the basic system configuration. This special information is then stored in battery-backed RAM so that it retains the Setup information when the power is turned off.
  • Page 74 CHAPTER 6 - BIOS SETUP Using Setup In general, you use the arrow keys to highlight items, press <Enter> to select, use the PageUp and PageDown keys to change entries, press <F1> for help and press <Esc> to quit. The following table provides more detail about how to navigate in the Setup program using the keyboard.
  • Page 75 CHAPTER 6 - BIOS SETUP In Case of Problems If, after making and saving system changes with Setup, you discover that your computer no longer is able to boot, the AwardBIOS™ supports an override to the CMOS settings which resets your system to its defaults. The best advice is to only alter settings, which you thoroughly understand.

  • Page 76: Main Menu

    CHAPTER 6 - BIOS SETUP 6.2. Main Menu Once you enter the Award BIOS CMOS Setup Utility, the Main Menu will appear on the screen. The Main Menu allows you to select from several setup functions and two exit choices. Use the arrow keys to select among the items and press <Enter>...
  • Page 77 CHAPTER 6 - BIOS SETUP Chipset Features Setup Use this menu to change the values in the chipset registers and optimize your system's performance. See section 6.5. for the details. Power Management Setup Use this menu to specify your settings for power management. See section 6.6. for the details.

  • Page 78: Standard Cmos Setup

    CHAPTER 6 - BIOS SETUP 6.3. Standard CMOS Setup The items in Standard CMOS Setup Menu are divided into 10 categories. Each category includes no, one or more than one setup items. Use the arrow keys to highlight the item and then use the <PgUp> or <PgDn> keys to select the value you want in each item.

  • Page 79: Ide Adapters

    CHAPTER 6 - BIOS SETUP Item Options Description All Errors Select the situation in which you No Errors Halt On All, but Keyboard want the BIOS to stop the POST All, but Diskette process and notify you All, but Disk/Key Displays amount Base Memory...

  • Page 80: Bios Features Setup

    CHAPTER 6 - BIOS SETUP 6.4. BIOS Features Setup This section allows you to configure your system for basic operation. You have the opportunity to select the system’s default speed, boot-up sequence, keyboard operation, shadowing and security. Virus Warning Allows you to choose the VIRUS Warning feature for IDE Hard Disk boot sector protection.
  • Page 81 CHAPTER 6 - BIOS SETUP CPU L2 Cache ECC Checking This item allows you to enable/disable CPU L2 Cache ECC checking. The choice: Enabled, Disabled. Quick Power On Self Test This category speeds up Power On Self Test (POST) after you power up the computer. If it is set to Enable, BIOS will shorten or skip some check items during POST.
  • Page 82 CHAPTER 6 - BIOS SETUP The choice: Normal, Fast. Typematic Rate Setting Keystroke repeat at a rate determined by the keyboard controller. When enabled, the typematic rate and typematic delay can be selected. The choice: Enabled, Disabled. Typematic Rate (Chars/Sec) Sets the number of times a second to repeat a keystroke when you hold the key down.
  • Page 83 CHAPTER 6 - BIOS SETUP OS Select For DRAM > 64MB Select the operating system that is running with greater than 64MB of RAM on the system. The choice: Non-OS2, OS2. Report No FDD For Win 95 Whether report no FDD for Win 95 or not. The choice: Yes, No.

  • Page 84: Chipset Features Setup

    CHAPTER 6 - BIOS SETUP 6.5. Chipset Features Setup This section allows you to configure the system based on the specific features of the installed chipset. This chipset manages bus speeds and access to system memory resources, such as DRAM and the external cache. It also coordinates communications between the conventional ISA bus and the PCI bus.
  • Page 85 CHAPTER 6 - BIOS SETUP SDRAM CAS Latency Time You can select CAS latency time in HCLK of 2/2 or 3/3. The system board designer should set the values in this field, depends on the DRAM installed specifications of the installed DRAM or the installed CPU.
  • Page 86 CHAPTER 6 - BIOS SETUP 8 Bit I/O Recovery Time The recovery time is the length of time, measured in CPU clocks, which the system will delay after the completion of an input/output request. This delay takes place because the CPU is operating so much faster than the input/output bus that the CPU must be delayed to allow for the completion of the I/O.
  • Page 87 CHAPTER 6 - BIOS SETUP AGP Aperture Size (MB) Select the size of the Accelerated Graphics Port (AGP) aperture. The aperture is a portion of the PCI memory address range dedicated for graphics memory address space. Host cycles that hit the aperture range are forwarded. Host cycles that hit the aperture range are forwarded to the AGP without any translation.

  • Page 88: Power Management Setup

    CHAPTER 6 - BIOS SETUP 6.6. Power Management Setup The Power Management Setup allows you to configure you system to most effectively save energy while operating in a manner consistent with your own style of computer use. Power Management This category allows you to select the type (or degree) of power saving and is directly related to the following modes: HDD Power Down Doze Mode...
  • Page 89 CHAPTER 6 - BIOS SETUP There are four selections for Power Management, three of which have fixed mode settings. Disable (default) No power management. Disables all four modes Min. Power Saving Minimum power management. Doze Mode = 1 hr. Standby Mode = 1 hr., Suspend Mode = 1 hr., and HDD Power Down = 15 min.
  • Page 90 CHAPTER 6 - BIOS SETUP MODEM Use IRQ Name the interrupt request (IRQ) line assigned to modem (if any) on your system. Activity of the selected IRQ always awakens the system. The choice: NA, 3, 4, 5, 7, 9, 10, 11. PM Timers The following four modes are Green PC power saving functions which are only user configurable when User Defined Power Management has been selected.
  • Page 91 CHAPTER 6 - BIOS SETUP PCI/VGA Act-Monitor When enabled, any video activity restarts the global timer for Standby mode. The choice: Enabled, Disabled Power On by Ring An input signal on the serial Ring Indicator (RI) line (an incoming call on the modem) awakens the system.
  • Page 92 CHAPTER 6 - BIOS SETUP Reload Global Timer Event When enabled, an event occurring on each device listed below restarts the global time for Standby mode. IRQ (3 – 7, 9 – 15), NMI Primary IDE 0 Primary IDE 1 Secondary IDE 0 Secondary IDE 1 FDD, COM, LPT Port...

  • Page 93: Pnp/Pci Configuration

    CHAPTER 6 - BIOS SETUP 6.7. PnP/PCI Configuration This section describes configuring the PCI bus system. PCI, or Personal Computer Interconnect, is a system which allows I/O devices to operate at speeds nearing the speed the CPU itself uses when communicating with its own special components.
  • Page 94 CHAPTER 6 - BIOS SETUP Reset Configuration Data Normally, you leave this field Disabled. Select Enabled to reset Extended System Configuration Data (ESCD) when you exit Setup if you have installed a new add-on and the system reconfiguration has caused such a serious conflict that the operating system can not boot.
  • Page 95 CHAPTER 6 - BIOS SETUP Primary / Secondary IDE INT# Each PCI peripheral connection is capable of activating up to four interrupts: INTA#, INTB#, INTC#, INTD#. By default, a PCI connection is assigned INTA#. Assigning INTB# has no meaning unless the peripheral device requires two interrupt services rather than just one.

  • Page 96: Defaults Menu

    CHAPTER 6 - BIOS SETUP 6.8. Defaults Menu Selecting “Defaults” from the main menu shows you two options, which are described below. Load BIOS Defaults When you press <Enter> on this item you get a confirmation dialog box with a message similar to: Load BIOS Defaults (Y/N) ? N Pressing ‘Y’...

  • Page 97: Integrated Peripherals

    CHAPTER 6 - BIOS SETUP 6.9. Integrated Peripherals IDE HDD Block Mode This allows your hard disk controller to use the fast block mode to transfer data to and from your hard disk drive (HDD) The choice: Enabled, Disabled. IDE Primary/Secondary Master/Slave PIO The four IDE PIO (Programmed Input/Output) fields let you set a PIO mode (0-4) for each of the four IDE devices that the onboard IDE interface supports.
  • Page 98 CHAPTER 6 - BIOS SETUP On-Chip Primary/Secondary PCI IDE The integrated peripheral controller contains an IDE interface with support for two IDE channels. Select Enabled to activate each channel separately. The choice: Enabled, Disabled. USB Keyboard Support Select Enabled if your system contains a Universal Serial Bus (USB) controller and you have a USB keyboard.
  • Page 99 CHAPTER 6 - BIOS SETUP UART 2 Duplex Select Select the value required by the IR device connected to the IR port. Full-duplex mode permits transmission in one direction only at a time. The Choice: Half, Full RxD, TxD Active This item allows you to determine the active of RxD, TxD.

  • Page 100: Supervisor/User Password Setting

    CHAPTER 6 - BIOS SETUP 6.10. Supervisor/User Password Setting You can set either supervisor or user password, or both of then. The differences between are: SUPERVISOR PASSWORD: can enter and change the options of the setup menus. USER PASSWORD: just can only enter but do not have the right to change the options of the setup menus.

  • Page 101: Exit Selecting

    CHAPTER 6 - BIOS SETUP 6.11. Exit Selecting Save & Exit Setup Pressing <Enter> on this item asks for confirmation: Save to CMOS and EXIT (Y/N)? Y Pressing “Y” stores the selections made in the menus in CMOS – a special section of memory that stays on after you turn your system off.

  • Page 102: Post Messages

    CHAPTER 6 - BIOS SETUP 6.12. POST Messages During the Power On Self-Test (POST), if the BIOS detects an error requiring you to do something to fix, it will either sound a beep code or display a message. If a message is displayed, it will be accompanied by: PRESS F1 TO CONTINUE, CTRL-ALT-ESC OR DEL TO ENTER SETUP 6.13.

  • Page 103: Error Messages

    CHAPTER 6 - BIOS SETUP 6.14. Error Messages One or more of the following messages may be displayed if the BIOS detects an error during the POST. This list includes messages for both the ISA and the EISA BIOS. CMOS battery has failed CMOS battery is no longer functional.
  • Page 104 CHAPTER 6 - BIOS SETUP Display type has changed since last BOOT Since last powering off the system, the display adapter has been changed. You must configure the system for the new display type. EISA configuration checksum error PLEASE RUN EISA CONFIGURATION UTILITY The EISA non-volatile RAM checksum is incorrect or cannot correctly read the EISA slot.
  • Page 105 CHAPTER 6 - BIOS SETUP Invalid EISA configuration PLEASE RUN EISA CONFIGURATION UTILITY The non-volatile memory containing EISA configuration information was programmed incorrectly or has become corrupt. Re-run EISA configuration utility to correctly program the memory. NOTE: When this error appears, the system will boot in ISA mode, which allows you to run the EISA Configuration Utility.
  • Page 106 CHAPTER 6 - BIOS SETUP Offending address not found This message is used in conjunction with the I/O CHANNEL CHECK and RAM PARITY ERROR messages when the segment that has caused the problem cannot be isolated. Offending segment This message is used in conjunction with the I/O CHANNEL CHECK and RAM PARITY ERROR messages when the segment that has caused the problem has been isolated.
  • Page 107 CHAPTER 6 - BIOS SETUP Should have EISA board but not found PLEASE RUN EISA CONFIGURATION UTILITY The board installed is not responding to the ID request, or no board ID has been found in the indicated slot. NOTE: When this error appears, the system will boot in ISA mode, which allows you to run the EISA Configuration Utility.
  • Page 108 CHAPTER 6 - BIOS SETUP Hard disk(s) fail (20) HDD initialization error. Hard disk(s) fail (10) Unable to recalibrate fixed disk. Hard disk(s) fail (08) Sector Verify failed. Keyboard is locked out - Unlock the key. Unlock the key. BIOS detect the keyboard is locked. P17 of keyboard controller is pulled low.

  • Page 109: Post Codes

    CHAPTER 6 - BIOS SETUP 6.15. POST Codes POST Description (hex) Test CMOS R/W functionality. Early chipset initialization: -Disable shadow RAM -Disable L2 cache (socket 7 or below) -Program basic chipset registers Detect memory -Auto-detection of DRAM size, type and ECC. -Auto-detection of L2 cache (socket 7 or below) Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 &...
  • Page 110 CHAPTER 6 - BIOS SETUP POST Description (hex) Reserved Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker. Reserved Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD &...
  • Page 111 CHAPTER 6 - BIOS SETUP POST Description (hex) 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute. 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead.
  • Page 112 CHAPTER 6 - BIOS SETUP POST Description (hex) Reset keyboard except Winbond 977 series Super I/O chips. Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Test 8254 Reserved Test 8259 interrupt mask bits for channel 1. Reserved Test 8259 interrupt mask bits for channel 2. Reserved Reserved Test 8259 functionality.
  • Page 113 CHAPTER 6 - BIOS SETUP POST Description (hex) 1. Program MTRR of M1 CPU 2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range. 3. Initialize the APIC for P6 class CPU. 4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical.
  • Page 114 CHAPTER 6 - BIOS SETUP POST Description (hex) Reserved Initialize PS/2 Mouse Reserved Prepare memory size information for function call: INT 15h ax=E820h Reserved Turn on L2 cache Reserved Program chipset registers according to items described in Setup & Auto-configuration table.
  • Page 115 CHAPTER 6 - BIOS SETUP POST Description (hex) Reserved Reserved Reserved 1. Switch back to text mode if full screen logo is supported. -If errors occur, report errors & wait for keys -If no errors occur or F1 key is pressed to continue: wClear EPA or customization logo.
  • Page 116 CHAPTER 6 - BIOS SETUP POST Description (hex) 1. Enable L2 cache 2. Program boot up speed 3. Chipset final initialization. 4. Power management final initialization 5. Clear screen & display summary table 6. Program K6 write allocation 7. Program P6 class write combining 1.
  • Page 118 A-46-427 LZS2451 021030 [010606]...

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