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Contec SPI-Q6700-LLVA User Manual

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SPI-Q6700-LLVA
PICMG 1.3 Full-size SBC
User's Manual
Version 1.0
2012.08

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Summary of Contents for Contec SPI-Q6700-LLVA

  • Page 1 SPI-Q6700-LLVA PICMG 1.3 Full-size SBC User’s Manual Version 1.0 2012.08...
  • Page 2 This page is intentionally left blank.

  • Page 3: Table Of Contents

    Index Table of Contents Chapter 1 - Introduction ..............1 1.1 Copyright Notice ...............2 1.2 Declaration of Conformity ..........2 1.3 About This User’s Manual ..........4 1.4 Warning ................4 1.5 Replacing the Lithium Battery .........4 1.6 Technical Support .............4 1.7 Warranty ................4 1.8 Packing List ...............5 1.9 Ordering Information ............6 1.10 Specifications ..............7...
  • Page 4 Index 3.3.3 ME Subsystem .............. 50 3.4 Boot Settings ..............52 3.5 Security ................54 3.6 Exit Options ..............55 3.7 Beep Sound codes list ............56 3.7.1 Boot Block Beep Codes ..........56 3.7.2 POST BIOS Beep Codes..........56 3.7.3 Troubleshooting POST BIOS Beep Codes ....57 3.8 AMI BIOS Checkpoints ...........58 3.8.1 Bootblock Initialization Code Checkpoints ....

  • Page 5: Chapter 1 Introduction

    Introduction Chapter 1 Introduction Chapter 1 - Introduction - 1 -...

  • Page 6: Copyright Notice

    This product has passed the CE test for environmental specifications when shielded cables are used for external wiring. We recommend the use of shielded cables. This kind of cable is available from Contec Solution. Please contact your local supplier for ordering information.
  • Page 7 RoHS Contec Solution Corp. certifies that all components in its products are in compliance and conform to the European Union’s Restriction of Use of Hazardous Substances in Electrical and Electronic Equipment (RoHS) Directive 2002/95/EC.

  • Page 8: About This User's Manual

    Introduction 1.3 About This User’s Manual This user’s manual provides general information and installation instructions about the product. This User’s Manual is intended for experienced users and integrators with hardware knowledge of personal computers. If you are not sure about any description in this booklet. Please consult your vendor before further handling.

  • Page 9: Packing List

    1.8 Packing List Packing List Before you begin installing your single board, please make sure that the following materials have been shipped: 1 x SPI-Q6700-LLVA PICMG 1.3 Full-size SBC 1 x Driver CD 1 x Quick Installation Guide Cable Kit...

  • Page 10: Ordering Information

    13 slots PICMG 1.3 backplane Note: SPI-Q6700-LLVA supports 1 x PCIex4. SPI-Q6701-LLVA supports 4 x PCIex1. PCIe x4 slot and PCIe x1 slot can’t work at the same time with the same BIOS version. Therefore, 2 BIOS versions are required to be applied as following configurations.

  • Page 11: Specifications

    Introduction 1.10 Specifications Form Factor PICMG 1.3 Full-size SBC Socket LGA1155 for Intel 32nm Sandy Bridge Processor processors (i7-2600 at 3.4GHz, i5-2400 at 3.1GHz, i3-2120 at 3.3GHz, or Pentium G850 at 2.9GHz) Chipset Intel® PCH Q67 2 x 240-pin Long-DIMM sockets, supporting DDR3 System Memory 1066/1333MHz, up to 8GB Integrated Intel HD Graphics 200...

  • Page 12: Board Dimensions

    Introduction 1.11 Board Dimensions 118.00 4.12 108.77 3.44 92.2 126.4 Unit:mm - 8 -...

  • Page 13: Installing The Cpu

    Introduction 1.12 Installing the CPU The LGA1155 processor socket comes with a lever to secure the processor. Please refer to the pictures step by step as below. 1. Push the lever down to unclip it and lift it. 2. Open the load plate. 3.

  • Page 14: Installing The Memory

    Introduction 1.13 Installing the Memory To install the Memory module, locate the Memory DIMM slot on the board and perform as below: 1. Hold the Memory module so that the key of the Memory module align with those on the Memory DIMM slot. 2.

  • Page 15: Chapter 2 Installation

    Installation Chapter 2 Installation Chapter 2 - Installation - 11 -...

  • Page 16: Block Diagram

    Installation 2.1 Block Diagram HiCORE-i67Q1 PICMG 1.3 Socket LGA1155 for Intel® Dual Channel DDR3 2 x 240-pin DDR3 i3-2120/ DIMM socket 1066/1333 MT/z i5-2400/ i7-2600 PCIex16 I/F PICMG 1.3 Processor PCIex16 GF (x4) Analog R.G.B. COM1 RS-232, COM2 RS-232/422/485 selectable COM1~2 COM1~2 10 x USB 2.0 ports...

  • Page 17: Jumpers And Connectors

    Installation 2.2 Jumpers and Connectors Jumpers/ Connectors Quick Reference Jumpers Label Description JBAT1 Protected RTC Setting JBAT2 Clear CMOS Setting JRS1 COM2 RS-232/422/485 Selection Connectors Label Description AUDIO1 AUDIO Connector COM1 RS-232 Connector COM2 RS-232/422/485 Connector DIO1 Digital I/O Connector Infrared Connector J2, J3, J5, J6 SATA Connectors...

  • Page 18: Jumpers & Connectors Location

    Installation 2.3 Jumpers & Connectors Location Socket LGA1155 JFAN2 JFAN1 JUSB3 JUSB1 JUSB2 DIO1 COM2 JUSB5 JRS1 JUSB4 COM1 JFRT1 JBAT2 JBAT1 AUDIO1 LAN1 KBM1 VGA1 LAN2 - 14 -...

  • Page 19: Jumpers

    Installation 2.4 Jumpers JBAT1: Protected RTS Setting (1) If the board refuses to boot due to inappropriate CMOS settings here is how to proceed to clear (reset) the CMOS to its default values. Connector type: 2.54mm pitch 1x3-pin headers Mode Keep Protected (Default) Clear CMOS JBAT2: Clear CMOS Setting (2)
  • Page 20 Installation Note: If you are unable to enter BIOS setup, turn the system on and off a few times. JBAT1 JBAT2 JRS1: COM2 RS-232 / 422 / 485 Selection (18) Connector type: 2.00mm pitch 2x3-pin headers. Mode RS-232 (Default) RS-422 RS-485 Short Open...

  • Page 21: Connectors

    Installation 2.5 Connectors JFRT1: Switches and Indicators (3) It provides connectors for system indicators that provides light indication of the computer activities and switches to change the computer status. Connector type: 2.54mm pitch 2x8-pin headers. Pin Description Pin Description Power LED+ PWRBTN+ Power LED- PWRBTN-...

  • Page 22: Pin Description

    Installation JUSB1~5: USB Ports (4, 5, 6, 7, 8) Connector type: 2.54mm pitch 2x5 pin-header, pin-10 is eliminated. Description. Description. USBD1- USBD2- USBD+ USBD2+ N/C (Key) JUSB2 JUSB3 JUSB4 JUSB1 JUSB5 JFAN1, 2: Fan Connectors (9), (11) Connector type: 2.54mm pitch 1x4-pin wafer connector. Description +12V FAN_CTL...
  • Page 23 Installation J7: ATX +12V Connector (10) J7 supplies the CPU operation ATX +12V (Vcore). Description Description +12V +12V J2, J3, J5, J6: Serial ATA Connectors (12, 13, 14, 15) Connector type: SATA connectors. Description - 19 -...
  • Page 24 Installation DIO1: Digital I/O Connector (16) Connector type: 2.54mm pitch 2x5-pin headers. Pin Description Pin Description DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 DIO1 COM2: RS-232 Port (17) Connector type: 2.54mm pitch 2x5-pin box headers. Description Description DCD# DSR# RTS# CTS# DTR#...
  • Page 25 Installation COM1: RS-232/422/485 Port (19) Connector type: 2.54mm pitch 2x7-pin box headers. Description Description DCD# DSR# RTS# CTS# DTR# 13 14 442TX+/ 485+ 422TX-/ 485- 422RX+ 422RX- COM1 - 21 -...
  • Page 26 Installation IR1: Infrared Connector (20) Connector type: 2.54mm pitch 1x5-pin headers. Description IRRX IRTX - 22 -...
  • Page 27 Installation J4: Parallel Port Connector (21) Connector type: 2.54mm pitch 2x13 box headers. Description Description STB# AFD# PTD0 ERROR# PTD1 INIT# PTD2 SLIN# PTD3 PTD4 PTD5 PTD6 PTD7 ACK# BUSY SELECT - 23 -...
  • Page 28 Installation AUDIO1: AUDIO Connector (22) Connector type: 2.00mm pitch 2x6-pin headers. Description Description LIN-L LIN-R LINE-JD GND_AU MICL MICR MIC-JD GND_AU LOUT-L LOUT-R FRONT-JD GND_AU AUDIO1 LAN1, 2: GbE Connectors (23), (24) Connector type: RJ-45 with LED indicators. LAN1 LAN2 - 24 -...
  • Page 29 Installation VGA1: Analog RBG Connector (25) Connector type: D-Sub 15-pin female. Description Description GREEN BLUE DDC_DATA HSYNC VSYNC DDC-CLK VGA1 - 25 -...
  • Page 30 Installation KBM1: Keyboard & Mouse Connector (26) Connector type: 6-pin Mini-DIN connector. Description KB Data MS Data VCC PS2 KB Clock MS Clock KBM1 - 26 -...

  • Page 31: The Installation Paths Of Cd Driver

    \GRAPHICS\INTEL_2K_XP_64\5313 AHCI \RAID\INTEL\6-series 10.1.0.1008 AUDIO \AUDIO\REALTEK_HD\WIN2K_XP_x86x64_R257 Windows 7 Chipset \CHIPSET\INF 9.2.0.1021 NET Framework \NET Framework \ETHERNET\INTEL\82583V\32 \ETHERNET\INTEL\82583V\64 \GRAPHICS\INTEL_WIN7_32\2291 Graphics \GRAPHICS\INTEL_WIN7_64\2291 AHCI \RAID\INTEL\6-series 10.1.0.1008 AUDIO \AUDIO\REALTEK_HD\Win7_R257 Management Engine Driver Please download the driver at Contec Solution ftp server. - 27 -...
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  • Page 33: Chapter 3 - Bios

    BIOS Chapter 3 BIOS Chapter 3 - BIOS - 29 -...

  • Page 34: Bios Introduction

    BIOS 3.1 BIOS Introduction The AMI BIOS provides a Setup utility program for specifying the system configurations and settings. The BIOS ROM of the system stores the Setup utility and configurations. When you turn on the computer, the AMI BIOS is immediately activated. To enter the BIOS SETUP UTILILTY, press “Delete”...

  • Page 35: System Date

    BIOS Key Commands BIOS Setup Utility is mainly a key-based navigation interface. Please refer to the following key command instructions for navigation process. Move to highlight a particular configuration screen from “←”“→” the top menu bar / Move to highlight items on the screen “↓”...

  • Page 36: Advanced Settings

    BIOS 3.2 Advanced Settings The “Advanced” screen provides setting options to configure ACPI, CPU, SATA, USB, Super IO and other peripherals. You can use “←” and “→” keys to select “Advanced” and use the “↓” and “↑” to select a setup item. Note: Please pay attention to the instructions at the upper-right frame before you decide to configure any setting of an item.

  • Page 37: Acpi Settings

    BIOS 3.2.1 ACPI Settings Press “Enter” on “ACPI Settings” and you will be able to set up ACPI configuration. Enable ACPI Auto Configuration Allow you to enable or disable BIOS ACPI Auto Configuration. Enable Hibernation Allow you to enable or disable system hibernation (OS/S4 Sleep State). This option may not be effective in some OSes.

  • Page 38: Cpu Configuration

    BIOS 3.2.2 CPU Configuration Press “Enter” on “CPU Configuration” to configure the CPU on the “CPU Configuration” screen. CPU Details Detail information including CPU manufacturer name, Processor Speed, Processor Stepping, Microcode Revision, Processor Core number, etc. Hyper-Threading Technology Enabled: activates the Hyper-Threading Technology for higher CPU threading speed.

  • Page 39: Hardware Prefetcher

    BIOS Active Processor Cores Number of cores to enable in each processor package. The choice: All, 1, 2 Limit CPUID Maximum Disable for Windows XP. The choice: Disabled, Enabled Execute Disable Bit Enable/Disable the Execute disable bit function. Hardware Prefetcher To turn on/off the MLC streamer prefetcher.

  • Page 40: Sata Configuration

    BIOS 3.2.3 SATA Configuration SATA Mode It allows you to select the operation mode for SATA controller. Serial-ATA Controller 0 Enable/ Disable Serial ATA Controller 0. The choice: Disable, Enhanced, Compatible Serial-ATA Controller 1 Enable/ Disable Serial ATA Controller 0. The choice: Disable, Enhanced - 36 -...

  • Page 41: Intel® Igd Swsci Opregion

    BIOS 3.2.4 Intel® IGD SWSCI OpRegion DVMT/ Fixed Memory This feature allows you to select the memory size of DVMT/BOTH operating mode. The choice: 256MB, 128MB, Maximum IGD – Boot Type This feature allows you to select the display device when you boot up the system.

  • Page 42: Intel® Trusted Execution Technology Configuration

    BIOS 3.2.5 Intel® Trusted Execution Technology Configuration Intel® TXT(LT) Support This item allows you to enable/disable the Intel TXT (LT) support. - 38 -...

  • Page 43: Usb Configuration

    BIOS 3.2.6 USB Configuration The menu is used to read USB configuration information and configure the USB setting. Legacy USB Support Enable support for legacy USB. Normally if this option is not enabled, any attached USB mouse or USB keyboard won’t be accessible until a USB compatible operating system is fully booted with all loaded USB drivers.

  • Page 44: Super Io Configuration

    BIOS Mass Storage Devices This item allows you to set up mass storage devices. The choice: Auto, Floppy, Forced FDD, Hard-Disk, CD-ROM 3.2.7 Super IO Configuration You can use this item to set up or change the Super IO configuration for FDD controllers, parallel ports and serial ports.

  • Page 45: Serial Port 1 Configuration

    BIOS Serial Port 1 Configuration Serial Port This item allows you to enable/disable Serial Port (COM). - 41 -...

  • Page 46: Serial Port 2 Configuration

    BIOS Serial Port 2 Configuration Serial Port This item allows you to enable/disable Serial Port (COM). Change Settings This item allows you to change the serial port IO port address and interrupt address. COMB RS-485 Autoflow This item allows you to enable serial port 2 auto flow control function. Auto flow control is used in RS-485 to control the signal transmitter automatically.

  • Page 47: Parallel Port Configuration

    BIOS Parallel Port Configuration Parallel Port Configuration This item allows you to enable/disable Parallel Port (LPT/LPTE). - 43 -...

  • Page 48: H/W Monitor

    BIOS 3.2.8 H/W Monitor The H/W Monitor lists out the temperature, fan speeds and system voltages being monitored. FAN1 Mode Setting Allow you to select the FAN control mode. FAN2 Mode Setting Allow you to select the FAN control mode. CPU/System Temperature Show you the current CPU/System fan temperature.

  • Page 49: Advanced Chipset Settings

    BIOS +3.3V / +5V / VBAT Show you the voltage level of the +3.3V, +5V standby and battery. VDIMM Show you the current VDIMM voltage. 3.3 Advanced Chipset Settings Select “Chipset” to enable CRID, access “North Bridge,” “South Bridge” and “ME Subsystem.”...

  • Page 50: North Bridge

    BIOS 3.3.1 North Bridge Vt-d Enable/Disable the Vt-d function. Initate Graphic Adapter This item allows you to select which graphics controller to use and set it as the primary boot device. The choice: IGD, PCI/IGD, PCI/PEG, PEG/IGD, PEG/PCI IGD Memory This item shows the information of the IGD (Internal Graphics Device) memory.

  • Page 51: South Bridge

    BIOS 3.3.2 South Bridge Normally, the south bridge controls the basic I/O functions, such as USB and audio. This screen allows you to access the configurations of I/Os. SMBus Controller SMBus Controller help The choice: Enabled, Disabled Wake on Lan from S5 Wake on Lan from S5 help The choice: Enabled, Disabled - 47 -...

  • Page 52: Pci Express Ports Configuration

    BIOS PCI Express Ports Configuration PCI Express Port 1/2/3/4/5/6/7/8 Enable/Disable the PCI Express Ports in the chipset. - 48 -...
  • Page 53 BIOS USB Configuration The USB Configuration menu is used to read USB configuration information and configure the USB settings. All USB Devices Use this item to enable or disable all USB devices. - 49 -...

  • Page 54: Me Subsystem

    BIOS 3.3.3 ME Subsystem Use the ME Subsystem menu to configure the Intel® Management Engine (ME) configuration options. ME Subsystem Use the ME Subsystem option to enable or disable the Intel® ME subsystem. The choice: Enabled, Disabled End of Post Message Use the End of Post Message option to enable or disable the end of post mes- sage of the ME Subsystem.
  • Page 55 BIOS Integrated Clock Chip Configuration ICC Enable This item allows you to enable or disable the current ICC. - 51 -...

  • Page 56: Boot Settings

    BIOS 3.4 Boot Settings Bootup Numlock State This item determines if the Numlock key is active or inactive at system start-up time. Quiet Boot This item can helps to select screen display when the system boots. The choice: Enabled, Disabled Boot Option Priorities This item allows you to select boot priorities for all boot devices.
  • Page 57 BIOS Boot Option #1 This item allows you to set the system boot priorities. - 53 -...

  • Page 58: Security

    BIOS 3.5 Security You can set administrator password by Security menu. - 54 -...

  • Page 59: Exit Options

    BIOS 3.6 Exit Options Use the option to exit BIOS settings, and save/discard any changes you made. Save Changes and Exit Exit system setup after saving the changes. Discard Changes and Exit Exit system setup without saving any changes. Discard Changes Discard changes done so far to any of the setup questions.

  • Page 60: Beep Sound Codes List

    BIOS 3.7 Beep Sound codes list 3.7.1 Boot Block Beep Codes Number of Beeps Description Insert diskette in floppy drive A: ‘AMIBOOT.ROM’ file not found in root directory of diskette in A: Flash Programming successful Floppy read error Keyboard controller BAT command failed No Flash EPROM detected Floppy controller failure Boot Block BIOS checksum error...

  • Page 61: Troubleshooting Post Bios Beep Codes

    BIOS 3.7.3 Troubleshooting POST BIOS Beep Codes Number of Beeps Description Reseat the memory, or replace with known good 1, 2 or 3 modules. Fatal error indicating a serious problem with the system. Consult your system manufacturer. Before declaring the motherboard beyond all hope, eliminate the possibility of interference by a malfunctioning add-in card.

  • Page 62: Ami Bios Checkpoints

    BIOS 3.8 AMI BIOS Checkpoints 3.8.1 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset, memory and other components before system memory is available. The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS (Note) Checkpoint...
  • Page 63 BIOS Both key sequence and OEM specific method are checked to determine if BIOS recovery is forced. If BIOS recovery is necessary, control flows tocheckpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information. Restore CPUID value back into register. The Bootblock- Runtime interface module is moved to system memory and control is given to it.

  • Page 64: Bootblock Recovery Code Checkpoints

    BIOS 3.8.2 Bootblock Recovery Code Checkpoints The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS (Note) Checkpoint...
  • Page 65 BIOS Erase the flash part. Program the flash part. The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h. - 61 -...

  • Page 66: Post Code Checkpoints

    BIOS 3.8.3 POST Code Checkpoints The POST code checkpoints are the largest set of checkpoints during the BIOS pre-boot process. The following table describes the type of checkpoints that may occur during the POST portion of the BIOS (Note) Checkpoint Description Disable NMI, Parity, video for EGA, and DMA controllers.
  • Page 67 BIOS Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. Detects the presence of PS/2 mouse. Detects the presence of Keyboard in KBC port. Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1.
  • Page 68 BIOS Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. USB controllers are initialized at this point. Initializes DMAC-1 & DMAC-2. Initialize RTC date/time. Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test.
  • Page 69 BIOS Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. Initialize runtime language module. Display boot option popup menu.

  • Page 70: Dim Code Checkpoints

    BIOS 3.8.4 DIM Code Checkpoints The Device Initialization Manager (DIM) gets control at various times during BIOS POST to initialize different system busses. The following table describes the main checkpoints where the DIM module is accessed (Note) Checkpoint Description Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0);...

  • Page 71: Acpi Runtime Checkpoints

    BIOS 0 = func#0, disable all devices on the BUS concerned. 2 = func#2, output device initialization on the BUS concerned. 3 = func#3, input device initialization on the BUS concerned. 4 = func#4, IPL device initialization on the BUS concerned. 5 = func#5, general device initialization on the BUS concerned.
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  • Page 73: Appendix

    Appendix Appendix Appendix - 69 -...

  • Page 74: Appendix A: I/O Port Address Map

    Appendix Appendix A: I/O Port Address Map Each peripheral device in the system is assigned a set of I/O port addresses which also becomes the identity of the device. The following table lists the I/O port addresses used. Address Device Description 0x00000000-0x0000000F Direct memory access controller 0x00000000-0x0000000F...
  • Page 75 Appendix 0x000000C0-0x000000DF Direct memory access controller 0x000000E0-0x000000EF Motherboard resources 0x000000F0-0x000000FF Numeric data processor 0x000001F0-0x00000177 ATA Channel 1 0x000001F0-0x000001F7 ATA Channel 0 0x000002F8-0x0000029F Motherboard resources 0x000002F8-0x000002FF Communications Port (COM2) 0x00000378-0x00000376 ATA Channel 1 0x00000378-0x0000037F Printer Port (LPT1) 0x000003B0-0x000003BB Intel(R) HD Graphics Family 0x000003B0-0x000003BB PCI bus 0x000003C0-0x000003DF Intel(R) HD Graphics Family 0x000003E0-0x00000CF7 PCI bus...

  • Page 76: Appendix B: Bios Memory Map

    Appendix 0x0000F070-0x0000F07F Intel(R) 6 Series/C200 Series Chipset Family 2 port Serial ATA Storage Controller - 1C08 0x0000F080-0x0000F083 Intel(R) 6 Series/C200 Series Chipset Family 2 port Serial ATA Storage Controller - 1C08 0x0000F090-0x0000F097 Intel(R) 6 Series/C200 Series Chipset Family 2 port Serial ATA Storage Controller - 1C08 0x0000F0A0-0x0000F0A3 Intel(R) 6 Series/C200 Series Chipset Family 2 port Serial ATA Storage Controller - 1C08 0x0000F0B0-0x0000F0B7 Intel(R) 6 Series/C200 Series Chipset Family 2...
  • Page 77 Appendix High Definition Audio Controller 0xFBC00000-0xFBC03FFF 0xFBC04000-0xFBC040FF Intel(R) 6 Series/C200 Series Chipset Family SMBus Controller - 1C2 0xFED00000-0xFED003FF High Precision Event Timer 0xFBC05000-0xFBC053FF Intel(R) 6 Series/C200 Series Chipset Family USB Enhanced Host Controller - 1C26 0xFBB40000-0xFBB5FFFF Intel(R) 82583V Gigabit Network Connection #7 0xFBA00000-0xFBAFFFFF Intel(R) 82583V Gigabit Network Connection #7 0xFBA00000-0xFBAFFFFF Intel(R) 6 Series/C200 Series Chipset Family PCI Express Root Port 2 - 1C12...

  • Page 78: Appendix C: Interrupt Request Lines (Irq)

    Appendix Appendix C: Interrupt Request Lines (IRQ) Peripheral devices use interrupt request lines to notify CPU for the service required. The following table shows the IRQ used by the devices on board. Level Function IRQ 0 System timer IRQ 1 Standard 101/102-Key or Microsoft Natural PS/2 Keyboard IRQ 3 Communications Port (COM2)

  • Page 79: Appendix D: Digital I/O Setting

    Appendix Appendix D: Digital I/O Setting Below are the source codes written in C, please take them for Digital I/O application examples. The default I/O address is 6Eh. #include <stdio.h> #include <dos.h> #include <conio.h> char APName[]= “\t\tSPI-Q6700-LLVA DIO Testing Program\n” “\t=========================================== \n”...
  • Page 80 Appendix //pg DIO as output //0:input 1:Output Index c0, GPIO3x Output pin control outportb(0x2e, 0xc0); /* select offset c0h */ outportb(0x2e+1, 0xff); delay(10); //pg DIO default LOW Index c1, GPIO3x Output Data value outportb(0x2e, 0xc1); /* select offset c1h */ outportb(0x2e+1, 0x00);...
  • Page 81 Appendix GP3xVal = 0; //DIO all low //pg DIO LOW outportb(0x2e, 0xc1); /* select offset c1h */ outportb(0x2e+1, 0x00); gotoxy(1,8); printf(“GP3x Status: Low \n”); break; default: break; //-printf( “Input: [%c] “, getkey); //DEBUG }while (getkey != 27); //ESC ascii==27 //pg all DIO as Input outportb(0x2e, 0xaa);...
  • Page 82 Appendix m_OutBuf=inportb(0x6C); if ( ( m_OutBuf&0x00000002) == 0 ) break; if ( i < 3999 ) outport(0x68,m_ECDATA); for ( i=0; i<=4000; i++ ) m_OutBuf=inportb(0x6C); if ( ( m_OutBuf&0x00000002) == 0 ) return 0x00000000; } if ( i > 3999 ) m_OutBuf=inportb(0x68); return 0xFFFFFFFF;...
  • Page 83 Appendix // break; if ( i > 3499 ) temp=inportb(0x68); return 0xFFFFFFFF; return 0xFFFFFFFF; //---------------------------------------------------------------------------- unsigned long ECU_Read_686C_RAM_BYTE( unsigned long ECUMe- mAddr ) unsigned long uDATA1,uDATA2,ECRamAddrH,ECRamAddrL; ECRamAddrL=ECUMemAddr%256; ECRamAddrH=ECUMemAddr/256; uDATA1=Process_686C_Command_Write(0x000000A3, ECRamAddrH ); if ( uDATA1==0xFFFFFFFF ) { return 0xFFFFFFFF; } uDATA1=Process_686C_Command_Write(0x000000A2, ECRamAddrL ); if ( uDATA1==0xFFFFFFFF ) { return 0xFFFFFFFF;...
  • Page 84 Appendix uDATA=Process_686C_Command_Write(0x000000A2, ECRamAddrL ); if ( uDATA==0xFFFFFFFF ) { return 0xFFFFFFFF;} uDATA=Process_686C_Command_Write(0x000000A5, ECUMemData ); if ( uDATA==0xFFFFFFFF ) { return 0xFFFFFFFF;} return 0x00000000; //---------------------------------------------------------------------------- unsigned char SMB_Byte_READ(int SMPORT, int DeviceID, int REG_IN- DEX) unsigned char SMB_R; outportb(SMPORT+02, 0x00); /* clear */ outportb(SMPORT+00, 0xff);...

  • Page 85: Appendix E: Watchdog Timer (Wdt) Setting

    Appendix Appendix E: Watchdog Timer (WDT) Setting WDT is widely used for industry application to monitor the activity of CPU. Application software depends on its own requirement to trigger WDT with adequate timer setting. Before WDT time-out, the functional normal system will reload the WDT.

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