Pioneer DVR-310-S Service Manual page 91

5
AK5381VT (MAIN ASSY : IC3101)
• 96kHz 24 bit ∆∑ ADC
Pin Arrangement (Top view)
AINR 1
AINL 2
CKS1 3
VCOM 4
AGND 5
VA 6
VD 7
DGNS 8
Pin Function
I/O
No. Pin Name
1 AINR I R ch analog input
2 AINL I L ch analog input
3 CKS1 I Mode select 1
4 VCOM O Common voltage output, bias voltage of VA/2 and ADC input
−
5 AGND Analog ground
−
6 VA Analog power supply, 4.5V to 5.5V
−
7 VD Digital power supply, 2.7 to 5.5V (fs = 4k to 48kHz), 3.0 to 5.5V (fs = 48k to 96kHz)
−
8 DGND Digital ground
9 SDTO O Audio serial data output, outputs "L" in the power down mode.
10 LRCK I/O Channel clock I/O, outputs "L" by master mode in the power down mode.
11 MCLK I Master clock input
12 SCLK I/O Audio serial data clock, outputs "L" by master mode in the power down mode.
13 PDN I Power down mode
14 DIF I
Audio interface format, "H" : 24 bit I2S compatibility, "L" : 24 bit MSB justify
15 CKS2 I Mode select 2
16 CKS0 I Mode select 0
5
6
16 CKS0
15 CKS2
14 DIF
13 PDN
12 SCLK
11 MCLK
10 LRCK
9 SDTO
"H": power up, "L": power down
DVR-310-S
6
7
Block Diagram
VA AGND VD
6 5 7
∆∑
Decimation
AINL 2
Modulator Filter
∆∑
Decimation
AINR 1
Modulator Filter
Voltage
VCOM
4
Reference
15 3 16
CKS2 CKS1 CKS0
Function
7
8
DGND MCLK
8 11
Clock
Divider
10 LRCK
12 SCLK
Serial I/O
9 SDTO
Interface
13 14
PDN DIF
91
8
A
B
C
D
E
F