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3.3.1.4
SDRAM Memory Device Refresh Register (MDREFR)
When configuring this register, follow the procedure recommended in the Intel
Processor Family Developer's Manual for initializing SDRAM.
MDREFR Recommended Settings:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Stand-alone Intel
1
00
1
X
0
0
0
NOTES:
1. SDCLK0 = MEMCLK / 4
2. Auto power-down (APD) enabled for all devices except synchronous flash-memory devices.
To identify the types used in the kit system, see
"Flash Memory" on page
43. See also the kit parts lists.
For more information on the APD function, see the MDREFR register description in the Memory Controller chapter of the Intel
PXA27x Processor Family Developer's Manual .
3. SDCLK1 = 65 MHz
4. Overridden by MDREFR[29]
5. One refresh every 7.62 µs. This value may change, depending on the presence of an expansion board with SDRAM mapped to
any of nSDCS<3:1>.
72
®
PXA270 Processor and Intel
2
0
1
0
0 1
X
0 1
Section 2.2.3, "Flash Memory and Boot ROM" on page 23
®
PXA270 Processorwith main board
3
4
1
1 X
1
0
®
Intel
PXA27x Processor Developer's Kit - User's Guide
®
PXA27x
1
E
8
7
6
5
4
3
2
5
0000 0001 1110
and
Section 2.4.2,
1
0
®
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