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UPI-41A 41AH 42 42AH USER'S MANUAL
BUS INTERFACE
The UPI-41A 41AH 42 42AH Microcomputer func-
tions as a peripheral to a master processor by using the
data bus buffer registers to handle data transfers The
DBB configuration is illustrated in Figure 5-1 The UPI
Microcomputer's 8 three-state data lines (D
nect directly to the master processor's data bus Data
transfer to the master is controlled by 4 external inputs
to the UPI
A
Address Input signifying command or data
0
CS Chip Select
RD Read strobe
WR Write strobe
Figure 5-1 Data Bus Register Configuration
The master processor addresses the UPI-41A 41AH
42 42AH Microcomputer as a standard peripheral de-
vice Table 5-1 shows the conditions for data transfer
Table 5-1 Data Transfer Controls
CS A
RD WR
0
0
0
0
1
Read DBBOUT
0
1
0
1
Read STATUS
0
0
1
0
Write DBBIN data set F
0
1
1
0
Write DBBIN command set
F
e
1
1
x
x
x
Disable DBB
56
CHAPTER 5
SYSTEM OPERATION
– D
) con-
7
0
231318– 32
Condition
0
e
1
1
Reading the DBBOUT Register
The sequence for reading the DBBOUT register is
shown in Figure 5-2 This operation causes the 8-bit
contents of the DBBOUT register to be placed on the
system Data Bus The OBF flag is cleared automatical-
ly
Reading STATUS
The sequence for reading the UPI Microcomputer's 8
STATUS bits is shown in Figure 5-3 This operation
causes the 8-bit STATUS register contents to be placed
on the system Data Bus as shown
Figure 5-2 DBBOUT Read
BUS CONTENTS DURING STATUS READ
ST
ST
ST
ST
7
6
5
4
D7
D6
D5
D4
Figure 5-3 Status Read
231318 –33
231318 –34
F
F
IBF
OBF
1
0
D3
D2
D1
D0
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