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UPI-41A 41AH 42 42AH USER'S MANUAL
The RESET input performs the following functions
Disables Interrupts
Clears Program Counter to Zero
Clears Stack Pointer
Clears Status Register and Flags
Clears Timer and Timer Flag
Stops Timer
Selects Register Bank 0
Sets PORTS 1 and 2 to Input Mode
DATA BUS BUFFER
Two 8-bit data bus buffer registers DBBIN and
DBBOUT serve as temporary buffers for commands
and data flowing between it and the master processor
Externally data is transmitted or received by the DBB
registers upon execution of an INput or OUTput in-
struction by the master processor Four control signals
are used
A
Address input signifying control or data
0
CS Chip Select
RD Read Strobe
WR Write Strobe
Transfer can be implemented with or without UPI pro-
gram interference by enabling or disabling an internal
UPI interrupt Internally data transfer between the
DBB and the UPI accumulator is under software con-
20
Figure 2-15 External Reset Configuration
trol and is completely asynchronous to the external
processor timing This allows the UPI software to han-
dle peripheral control tasks independent of the main
processor while still maintaining a data interface with
the master system
Configuration
Figure 2-16 illustrates the internal configuration of the
DBB registers Data is stored in two 8-bit buffer regis-
ters DBBIN and DBBOUT DBBIN and DBBOUT
may be accessed by the external processor using the
WR line and the RD line respectively The data bus is
a bidirectional three-state bus which can be connected
directly to an 8-bit microprocessor system Four con-
trol lines (WR RD CS A
processor to transfer data to and from the DBBIN and
DBBOUT registers
An 8-bit register containing status flags is used to indi-
cate the status of the DBB registers The eight status
flags are defined as follows
) are used by the external
0
OBF Output Buffer Full
This flag is automatically set when the UPI-Micro-
computer loads the DBBOUT register and is cleared
when the master processor reads the data register
IBF Input Buffer Full
This flag is set when the master processor writes a
character to the DBBIN register and is cleared
when the UPI INputs the data register contents to
its accumulator
231318 –20
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