Sharp FO-DC600 Service Manual page 66

FO-DC600U
HD6417706F133 (IC24) Terminal description (2/2)
PIN I/O Name
101 I/I/O IOIS16-/PTD[5]
102 O BACK-
103 I BREQ-
104 i WAIT-
105 O/I/O DACK0/PTE[0]
106 O/I/O DACK1/PTE[1]
107 O/I/O DRAK0/PTE[2]
108 O/I/O DRAK1/PTE[3]
109 I/O AUDATA[0]/PTF[0] AUD data/ input/output port F
110 I/O AUDATA[1]/PTF[1] AUD data/ input/output port F
111 I/O AUDATA[2]/PTF[2] AUD data/ input/output port F
112 I/O AUDATA[3]/PTF[3] AUD data/ input/output port F
113 O/I/O AUDSYNC-/PTF[4] AUD synchronous/ input/output port F
114 I TDI/PTG[0]
115 — Vss
116 I TCK/PTG[1]
117 — Vcc
118 I TMS/PTG[2]
119 I TRST-/PTG[3]
120 O/I/O TDO/PTF[5]
121 O/I/O ASEBRKAK-/PTF[6] ASE break acknowledge(H-UDI)/input/output port F
122 I ASEMD0-*
123 — Vcc-PLL1*
124 — CAP1
125 — Vss-PLL1*
126 — Vss-PLL2*
127 — CAP2
128 — Vcc-PLL2*
129 I MD1
130 — Vss
131 O XTAL
132 I EXTAL
133 O/I/O STATUS0/PTE[4]
134 O/I/O STATUS1/PTE[5]
135 I/O TCLK/PTE[6]
136 O/I/O IRQOUT-/PTE[7]
137 — VssQ
138 I/O CKIO
Notes: *1 Must be connected to the power supply even when the RTC is not used.
*2 Must be connected to the power supply even when the on-chip PLL circuits are not used.(EXcept in hardware standby mode.)
*3 Must be high level when the user system is used independently without using the emulator or H-UDI.
1. Except in hardware standby mode, all Vcc/Vss pins must be connected to the system power supply. (Supply power constantly.) In hardware
standby mode, power must be supplied at least to Vcc-RTC and Vss-RTC. If power is not supplied to Vcc and Vss pins other than Vcc-RTC
and Vss-RTC, hold the CA pin low.
2. A1, A2, A3, A7, A12, B1, C4, C7, D1, D2, D4, D7, D14, D15, E1, E2, E3, E4, F14, F17, G17, H14, H15, K14, P14, R10, T13, T15, T16, U11,
U15, and U16 must be connected to Vss.
Function
IOIS16(PCMCIA)/input port D
Bus acknowledge
Bus request
Hardware wait request
DMA acknowledge 0/input/output port E
DMA acknowledge 1/input/output port E
DMA request acknowledge/input/output port E
DMA request acknowledge/input/output port E
Data input(H-UDI)/input port G
Internal power supply (0 V)
Clock(H-UDI)/input port G
Internal power supply (1.9 V)
Mode select(H-UDI)/input port G
Reset(H-UDI)/input port G
Data output(H-UDI)/input/output port F
3
ASE mode(H-UDI)
2
PLL1 power supply (1.9 V)
PLL1 external capacitance pin
2 PLL1 power supply (0 V)
2 PLL2 power supply (0 V)
PLL2 external capacitance pin
2 PLL2 power supply (1.9 V)
Clock mode setting
Internal power supply (0 V)
Clock oscillator pin
External clock/crystal oscillator pin
Processor status/input/output port E
Processor status/input/output port E
TMU or RTC clock input/output/input/output port E
Interrupt request notification/output/input/output port E
Input/output power supply (0 V)
System clock input/output
PIN I/O Name
139 — VccQ
140 O TxD0/SCPT[0]
141 I/O SCK0/SCPT[1]
142 O TxD2/SCPT[2]
143 I/O SCK2/SCP[3]
144 O/I/O RTS2-/SCPT[4]
145 I RxD0/SCPT[0]
146 I RxD2/SCPT[2]
147 I CTS2-/IRQ5/SCPT[5]
148 — Vss
149 I RESETM-
150 — Vcc
151 I/I/I/O IRQ0/IRL0-/PTH[0] External interrupt request/input/output port H
152 I/I/I/O IRQ1/IRL1-/PTH[1] External interrupt request/input/output port H
153 I/I/I/O IRQ2/IRL2-/PTH[2] External interrupt request/input/output port H
154 I/I/I/O IRQ3/IRL3-/PTH[3] External interrupt request/input/output port H
155 I/I/O IRQ4/PTH[4]
156 — VssQ
157 I NMI
158 — VccQ
159 I AUDCK/PTG[4]
160 I/I/O DREQ0-/PTH[5]
161 I/I/O DREQ1-/PTH[6]
162 I ADTRG-/PTG[5]
163 I MD0
164 I MD2
165 I RESETP-
166 I CA
167 I MD3
168 I MD4
169 I MD5
170 — AVss
171 I AN[0]/PTJ[0]
172 I AN[1]/PTJ[1]
173 I/O/I AN2[2]/DA[1]/PTJ[2] A/D converter input/ D/A converter output/ input port J
174 I/O/I AN3[3]/DA[0]/PTJ[3] A/D converter input/ D/A converter output/ input port J
175 — AVcc
176 — AVss
5 – 4
Function
Input/output power supply (3.3 V)
SCI transmit data 0/SC port
SCI clock 0/SC port
SCIF transmit data 2/SC port
SCIF clock 2/SC port
SCIF transmit request 2/SC port
SCI receive data 0/SC port
SCIF receive data 2/SC port
SCIF transmit clear/external interruption request/SC port
Internal power supply (0 V)
Manual reset request
Internal power supply (1.9 V)
External interrupt request/input/output port H
Input/output power supply (0 V)
Nonmaskable interrupt request
Input/output power supply (3.3 V)
AUD clock/input port G
DMA request/input/output port H
DMA request/input/output port H
Analog trigger/input port G
Clock mode setting
Clock mode setting
Power-on reset request
Chip activate/hardware standby request
Area 0 bus width setting
Area 0 bus width setting
Endian setting
Analog power supply (0 V)
A/D converter input/input port J
A/D converter input/input port J
Analog power supply (3.3 V)
Analog power supply (0 V)