Circuit Diagram - LG KP270 Service Manual

6. CIRCUIT DIAGRAM

1 2 3
1V8_SD
BASE BAND PROCESSOR
A
VBAT
F3
BAT_ID M0
G4
RF_TEMP M1
E2
M2
R102 D1
JACK_TYPE M3
F4
390K
M4
E3
(1%)
M5
D3
M6
E4
M7
B D2
M8
D4
M9
F5
R103
R131 PCB_VERSION M10
100K
24000ohm
(1%) P4
(1%) PAOUT1_1
M8
PA_LEVEL PAOUT1_2
L5
2G_IP BB_I
M5
2G_IN BB_IX
M4
R131 REVISION
2G_QP BB_Q
P5
2G_QN BB_QX
24K ohm REV_1.0 AD15
3G_RX_IP ARXP_I
AE16
3G_RX_IN ARXN_I
AD17
3G_RX_QP ARXP_Q
AE17
3G_RX_QN ARXN_Q
AE13
3G_TX_IP ATXP_I
AD13
3G_TX_IN ATXN_I
AE14
3G_TX_QP ATXP_Q
AD14
3G_TX_QN ATXN_Q
C AD11
3G_VGC_TX ATX_VGA_DAC
AE11
ATX_PA_DAC
AE12
ATX_PA_ADC
R104 22K
AD12
AIREF
(1%)
Y8
TXON_PA T_OUT0
AB7
T_OUT1
V9
ANT_SEL1 T_OUT2
AA8
MLED_CLDO_CTRL T_OUT3
W9
_EOC T_OUT4
V8
MMC_DETECT T_OUT5
AB3
PA_MODE T_OUT6
AB4
ANT_SEL2 T_OUT7
W8
ANT_SEL3 T_OUT8
AC1
DSR T_OUT9
AB5
JACK_DETECT T_OUT10
AB1
TA_DETECT T_IN0
AA3
CHG_EN T_IN1
AA1
2G_EN RF_STR0
AC3
_PPR RF_STR1
D 1V8_SD W5
2G_DATA RF_DATA
W7
2G_CLK RF_CLK
W6
AFC
E8
CLKOUT0
D7
26MHZ F26M
A6
CLK26M
W10
C136
MMC_CMD MMCI1_CMD
AB6
U101 NC7SZ74L8X
0.1u MMC_D0 MMCI1_DAT[0]
1 8 AB9
_PR VCC MMC_CLK MMCI1_CLK
Y11
MMC_D1 MMCI1_DAT[1]
2 7 V10
_CLR CK MMC_D2 MMCI1_DAT[2]
AA9
MMC_D3 MMCI1_DAT[3]
3 6 AB17
AFC Q D MMCI2_CMD
AA17
MMCI2_DAT[0]
4 5 V14
GND _Q MOTOR_EN MMCI2_CLK
F9
RPWRON_DBB FWP
W17
USB_OEn IRDA_TX
AB19
SLIDE_DETECT IRDA_RX
Y5
JTAG0_TDO
E Y3
JTAG0_TDI
Y6
JTAG0_TMS
AA5
JTAG0_TCK
V7
JTAG0_TRST_N
V4
JTAG0_RTCK
2V62_VIO AD2
JTAG1_TDI
2V62_VIO AE5
JTAG1_TRST_N
AE4
JTSG1_TMS
AE2
JTAG1_TDO
AE6
JTAG1_RTCK
TP110 A4
R111 R112 A_RESET RST_N
A5
1K 1K BOOT_CFG[0]
A3
BOOT_CFG[1]
AA7
TRIG_IN TRIG_IN
Y7
MON1
Y9
MON2
D16
R114
R113 TRACESYNC
G9
DNI TRACECLK
10K G10
PIPESTAT[2]
F
H10
PIPESTAT[1]
D13
PIPESTAT[0]
D12
TRACEPKT[0]
E10
TRACEPKT[1]
B7
TRACEPKT[2]
D9
TRACEPKT[3]
D11
TRACEPKT[4]
G7
TRACEPKT[5]
E9
TRACEPKT[6]
D8
TRACEPKT[7]
H19
BFCLKO ESIF_CLK
AD9
_WR ESIF_WRN
J19
_WAIT ESIF_WAITN
AD8
ADV_A15 ESIF_ADVN
AE7
_CS3 ESIF_CSN
AE8
_RD ESIF_RDN
G
MODEL difference
R126 DNI
KP270 = 900_1800_1900_W2100
H
R127 DNI
KP275d = 850_1800_1900_W2100_850_FM_VT
R128 DNI
KP275c = 900_1800_1900_W2100_850_FM_VT
R129 DNI
KP275x = 900_1800_1900_W2100_900_FM_VT
1 2 3
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
4 5 6
2V62_VIO 2V11_RTC 2V5_VAUDB
1V35_CORE
2V9_VSIM 1V35_VPLL 2V5_VAUDA
2V9_VMME
2V11_RTC
R101
VBACKUP
10K
(1%)
VREFN
U103
PMB8868
VMIC_P
C145
39p
C146
39p
1V8_SD
C147
39p C148 R123
G2 G2
R124
10 10
G1 G1 0
5 5
47K 39p
L101 L102
100nH 100nH L103 L104
100nH 100nH
C150 C151
39p 39p
4 5 6
7 8 9
2V5_VAUDB 1V35_CORE 2V62_VIO
1V35_VPLL 1V8_SD
ADD(0:26)
G15
MEM_A[0] ADD(0)
E16
MEM_A[1] ADD(1)
G16
ADD(2)
MEM_A[2]
F14
ADD(3)
MEM_A[3]
E15
ADD(4)
MEM_A[4]
F16
MEM_A[5] ADD(5)
G14
MEM_A[6] ADD(6)
E14
MEM_A[7] ADD(7)
E13
ADD(8)
MEM_A[8]
F13
ADD(9)
MEM_A[9]
G13
ADD(10)
MEM_A[10]
E11
ADD(11)
MEM_A[11]
E12
MEM_A[12] ADD(12)
G12
MEM_A[13] ADD(13)
G11
ADD(14)
MEM_A[14]
F11
ADD(15)
MEM_A[15]
J18
ADD(16)
MEM_A[16]
L15
ADD(17)
MEM_A[17]
H18
MEM_A[18] ADD(18)
F19
MEM_A[19] ADD(19)
J15
MEM_A[20] ADD(20)
G18
ADD(21)
MEM_A[21]
K16
ADD(22)
MEM_A[22]
D19
ADD(23)
MEM_A[23]
K15
ADD(24)
MEM_A[24]
H16
MEM_A[25] ADD(25)
J16
MEM_A[26] ADD(26) DATA(0:15)
N19
DATA(0)
MEM_AD[0]
N18
DATA(1)
MEM_AD[1]
T15
DATA(2)
MEM_AD[2]
R19 DATA(3)
MEM_AD[3]
N17 DATA(4)
MEM_AD[4]
M19 DATA(5)
MEM_AD[5]
M18
DATA(6)
MEM_AD[6]
M17
DATA(7)
MEM_AD[7]
T18
DATA(8)
MEM_AD[8]
R18
DATA(9)
MEM_AD[9]
R16 DATA(10)
MEM_AD[10]
P16 DATA(11)
MEM_AD[11]
L18 DATA(12)
MEM_AD[12]
M15
DATA(13)
MEM_AD[13]
P18
DATA(14)
MEM_AD[14]
L16 DATA(15)
MEM_AD[15]
K18
MEM_CS0_N _NAND_CS
L17
MEM_CS1_N _RAM_CS
M16
MEM_CS2_N
N15
MEM_CS3_N _CS3 PM_VCXO_EN
G17
MEM_CSA0_N ADD(27)
H15
MEM_CSA1_N ADD(28)
H14
MEM_CSA2_N ADD(29)
R107
H13
MEM_CSA3_N ADD(30)
3300
H9
FCDP_RBN FCDP
Y19
MEM_WAIT_N _WAIT
P17
MEM_ADV_N ADV_A15
Y18
MEM_RD_N _RD
K17
MEM_WR_N _WR
D18 R110 10
MEM_BFCLKO1 BFCLKO
E17
MEM_BFCLKO2 SDCLKI
C18
MEM_SDCLKO SDCLKO
F17
MEM_BC0_N _BC0
H17
MEM_BC1_N _BC1
F15
MEM_BC2_N LDQS
F12
MEM_BC3_N UDQS
H12
MEM_RAS_N _RAS
D14
MEM_CAS_N _CAS
H11
MEM_CKE CKE
B1
CLK32K CLK32K
D5
F32K
D6
OSC32K
E6
RESET_N _RESET C141 C142
R2
RSTOUT_N 18p 18p
F7
RTC_OUT RTC_OUT
T1
SPCU_RQ_IN0
R3
SPCU_RQ_IN1 BT_VCXO_EN
T3
SPCU_RC_OUT0 PM_VCXO_EN
V1
SPCU_RQ_IN2
J4
VREFP VREFN
C143 220n
J5
IREF
C19
GPIO[0] R115
B19
GPIO[1] 22K
B18
(1%)
GPIO[2]
A18
GPIO[3]
C17
GPIO[4]
A17
GPIO[5]
B16
GPIO[6]
A15
GPIO[7] 3G_LD
B15
GPIO[8]
A14
GPIO[9]
B5
GPIO[10] 3G_MASTERON
B13
GPIO[11]
A13
GPIO[12]
A12
GPIO[13]
B12 TP111
GPIO[14]
A11
GPIO[15] 3G_PA_MODE1
A10
GPIO[16] ANT_SEL4
B10
GPIO[17] ANT_SEL5
A9
GPIO[18] ANT_SEL6
A8
GPIO[19]
1V8_SD
1V8_SD 1V8_SD
R130 R125
47K 47K
7 8 9
- 125 -
10 11 12
1G NAND(Large Block x16bit) +512M DDR SDRAM
ADD(16:28)
U102 TY9000A000TMGF TP102
ADD(0:15)
ADD(0) TP101 L4 D4 ADD(16)
DQ0 A0
ADD(1) M4 E4 ADD(17)
DQ1 A1
ADD(2) N4 F4 ADD(18)
DQ2 A2
ADD(3) L5 G4 ADD(19)
DQ3 A3
ADD(4) M5 G8 ADD(20)
DQ4 A4
ADD(5) N5 F8 ADD(21)
DQ5 A5
ADD(6) M6 E8 ADD(22)
DQ6 A6
ADD(7) N6 D8 ADD(23)
DQ7 A7
ADD(8) M7 D9 ADD(24)
DQ8 A8
ADD(9) N7 G7 ADD(25)
DQ9 A9
ADD(10) L8 G5 ADD(26)
DQ10 A10
ADD(11) M8 F7 ADD(27)
DQ11 A11
ADD(12) N8 E7 ADD(28)
DQ12 A12 DATA(0:15)
ADD(13) L9
DQ13
ADD(14) M9 P10 TP103 DATA(0)
DQ14 IO1
ADD(15) N9 N10 DATA(1)
DQ15 IO2
M10 DATA(2)
IO3
A1 L10 DATA(3)
NC1 IO4
A2 F10 DATA(4)
NC2 IO5
A3 E10 DATA(5)
NC3 IO6
A10 D10 DATA(6)
NC4 IO7
A11 C10 DATA(7)
NC5 IO8
A12 N11 DATA(8)
NC6 IO9
B1 M11 DATA(9)
NC7 IO10
B2 L11 DATA(10)
NC8 IO11
B3 K11 DATA(11)
NC9 IO12
B10 G11 DATA(12)
NC10 IO13
B11 F11 DATA(13)
NC11 IO14
B12 E11 DATA(14)
NC12 IO15
C1 D11 DATA(15)
NC13 IO16
C2
NC14
C3 K2
NC15 NC46
C11 K4
NC16 NC47
C12 K5
NC17 NC48
D1 K8
NC18 NC49
D2 K9
NC19 NC50
D3 K10
NC20 NC51
E2 L2
NC21 NC52
E9 M2
NC22 NC53
F2 N2
NC23 NC54
F9 P1
NC24 NC55
G6 P2
NC25 NC56
G9 P3
NC26 NC57
G10 P11
NC27 NC58
H3 P12
NC28 NC59
H4 R1
NC29 NC60
H5 R2
NC30 NC61
H6 R3
NC31 NC62
H7 R10
NC32 NC63
H8 R11
NC33 NC64
H9 R12
NC34 NC65
H11 T1
NC35 NC66
J2 T2 1V8_SD
NC36 NC67
J3 T3
NC37 NC68
1V8_SD J4 T10
NC38 NC69
T11
J5
NC39 NC70
J6 T12
NC40 NC71
J7 1V8_SD
NC41
1V8_SD J8
NC42
R106 10K
J9 N3
NC43 _WP
J10 F3 TP104
NC44 _RE _RD R108
J11 G3 TP105
C133 C134 C135
NC45 _CE _NAND_CS 10K
D5
TP106
_CS _RAM_CS
0.1u 0.1u 0.1u
1V8_SD C4 E3
VCCD1 RY__BY
C8 C6
C137 C138 VCCD2 _CLK SDCLKI
P6 C7
0.1u 0.1u VCCD3 CLK SDCLKO
D7 TP107
CKE CKE
P4 K3 TP108
VCCQD1 CLE ADD(17)
P8 L3
VCCQD2 ALE ADD(16)
M3 TP109
_WEN _WR
H2 E6
VCCN1 _CAS _CAS
F6
_RAS _RAS
C5 L6
C139 C140 VSS1 LDQS LDQS
C9 L7
0.1u 0.1u VSS2 UDQS UDQS
G2 K7
VSS3 UDQM _BC1
H10 K6
VSS4 LDQM _BC0
P5 D6
VSS5 _WED _WR
P7 E5
VSS6 BA0 ADD(29)
P9 F5
VSS7 BA1 ADD(30)
X101 MC-146_12_5PF
3
4
1 2
32.768KHz
OJ101 OJ102
CTS
12
RTS
TP113 11
DSR DSR
10
USB_DP UTXD
NC4
9
USB_DM
NC3 URXD
8
USB_VCHG
NC2 PWR
7
VBAT VBAT VBAT
6
TP114
RPWRON_EN ON_SW ON_SW
5
VCHG NC1 VCHAR
TP115 4
UART_TX TX
TX
TP116 3
UART_RX
RX RX
2
GND GND
1
2.5G 3G
UART
10 11 12
LGE Internal Use Only
A
B
C
D
FCDP
E
F
G
H