Sharp ER-A440 Service Manual page 19

6. SSP circuit
1) Block diagram
This is the circuit employed to do the Special Service Preset(SSP).
(Block diagram)
NMI
A0~23
D0~D7
CPU
(MPCA7 block diagram)
BAR 0
D0~
D7
BAR N
REGCS
Decode
A23~
A0
Control signal
ROMCS
1
Upper bits
SSPRQ
MPCA7
Fig. 6-1
Comparator
Coincide
O
N
Coincide
SPE
(Enable register)
Fig. 6-2
A19 A18 A17 A16 A15
Intermediate bits
Don't care for "-----."
As the address detection system, the brake address register compari-
son system is employed though the mapping system was employed
in the conventional monitor RAM. The address registerlocated in
MPCA is always compared with the system address bus to monitor
and generate NMI signal at a synchronized timing and togo to NMI
exception process.
In the exception process routine service routine, the entry address is
checked to go to SSP sub routine.
Entry to the break address register (BAR) is performed through ad-
dress FFFF00H or later decoded in MPCA7.
2) SSP register
The break address register (BAR) is accessed through direct address
of FFFF00H~FFFFFFH. Entry number is 32 entry.
SSPRQ
(NMI)
Each BAR is composed of 4 byte address. Bit composition is as
follows:
A8 A7
2
Lower bits
< BAR composition >
Fig. 6-4
is the enable register. The entry registers of the break address are
assigned to
bit position, writing to
corresponding area is 1MB space of ROS1 and ROS2.
4 – 12
7
FFFF00
1
H
2
1
3
2
4
3
4
5
6
7
Fig. 6-3
A2
EN
3
Enable register
EN (bit7) = 1 Enable
, , and . Each bit of address corresponds to each
, , and is performed without shifting. The
0
BAR0
BAR1
BAR2
4
= 0 Inhibit