Sharp ER-A440 Service Manual page 18

RAM area memory map
100000H
1C0000H
RAS1 (Not use)
1F0000H
RAS2 64K Byte
200000H
280000H
400000H
BFFFFFH
Note: RAS2 signal is formed as OR in the image area of 0 page.
(lower32KB).
I/O area memory map
00FF80H
00FFA0H
MCR1 (NOT USE)
MCR2 (NOT USE)
00FFC0H
00FFD0H
00FFE0H
00FFE8H
00FFF0H
00FFFFH
Note 1: MPCCS signal is the base signal for MPCA7 internal reg-
isterdecoding, and does not exist as an internal signal.
Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC
(optionperipheral controller) using the base signal OPTCS
for optiondecoding. They does not exist as external sig-
nals.
NOT USE
RAS3
512K Byte
(OPTION)
(MAX 2MB)
NOT USE
Fig. 5-4
(*1)
MPCCS
NOT USE
(*2)
OPCCS1
(*2)
OPCCS2
NOT USE
NOT USE
NOT USE
Fig. 5-5
2) Block diagram
Data bus
CPU MPCA7
Address bus
ROM control
Address
Address
A23~A14
decorder
(IPLON)
IPLON: IPL board detection signal incorporated in the option slot.
Note used in the ER-A445P. (Not used)
Access is performed with two ROM chip select signals ROS1 and
ROS2, which decode 512KB address area respectively to access-
max. 4MB ROM.
RAM control
Address
A23~A14
DOI D
S8F CK
RESET
Access is performed with two RAM chip select signals, RAS2 and
RAS3. The control register in MPCA7 allows selection of pageimage
memory area. (RAS1 is selected for initializing.)
: For 0 page image area, selection between RAS2 and RAS3 can
bemade with the control register. The 0 page control registerper-
forms initializing at the timing of no stack processimmediately
after resetting.
4 – 11
ROS1
ROM1
(STANDARD)
(OPTION)
RAM1
RAS2 RAS3
RAM2
Fig. 5-6
C80000H~CFFFFFH
C00000H~C7FFFFH
000000H~007FFFH
MPCA7
Fig. 5-7
200000H~3FFFFFH
1C0000H~1DFFFFH
Address
decorder
008000H~
00F7FFH
*1
1E0000H~1FFFFFH
Q
Control register
R
MPCA7
Fig. 5-8
RAM
ROS2
ROS1
RAS3
RAS1
RAS2