Sharp ER-A440 Service Manual page 17

Electronic cash register
Hide thumbs Also See for ER-A440:
Table of Contents

Advertisement

This circuit monitors +24V supply voltage.
The voltage at the (–) pin of the comparator IC3A is always main-
tained to 5.1V by means of the zener diode ZD2, while +24V supply
voltage is divided through the resistors R12, R13, and R14, and is
applied to the (+) pin. When normal +24V is in supply, 6.8V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +5.1V, which
causes POFF to go low, thus predicting the power-off situation.
VDD
14
9
RESETS
CKDC8
10
IC10C
74HC00S
R123
C88
10K
1000P
STOP
The STOP signal from the CPU is converted into the RESETS signal
by the CKDC6.
The RESETS signal from the CKDC8 is converted into the RESET
signal at the gate backed-up by the VRAM power, performing the
system reset.
5. Memory control
1) Memory map
All range memory map
000000H
1C0000H
C00000H
Expansion I/O area (1M byte)
FFFFFFH
( 1)
"Internal I/O" means the registers in the H8/510.
( 2)
"External I/O" means the base system I/O area to be ad-
dressed in page 0.
( 3)
"Memory image area" means the lower 32KB of ROM area
which is projected to 000000H ~ 007FFFH for allowing reset
start and other vector addressing, or the lower 32KB of RAM
area which is projected to 008000H ~ 00FE7FH for allowing 0
page addressing of work RAM area.
( 4)
"Expansion I/O" means expansion I/O device area which isad-
dressed to area other than page 0.
VDD
14
4
RAS3
6
5
VDD
IC10B
74HC00S
14
1
8
3
/RESET
2
IC10A
74HC00S
C86
C87
1000P
1000P
Internal I/O
(*1)
External I/O
(*2)
Memory image area
(*3)
RAM area
(10M byte)
ROM area
(3M byte)
Fig. 5-1
0 page memory map
000000H
004000H
008000H
/(RAS3./RESET)
00FFFFH
1BFFFFH
1FFFFFH
ROM image area: Image is formed in ROM area address
C00000H to C07FFFH. This area is identical to IPL ROM area
which will beseparately developed.
RAM image area: Image is formed in RAM area address 1F0000H
to 1F7E7FH. ( Note)
Note: Image can be formed in lower 32KB of RAS2.
ROM area memory map
4 – 10
ROM image area
32KB
RAM image area
slightly smaller than32KB
00F800H
00FE80H
NOT USE
00FF80H
RAM area
00FFFFH
Fig. 5-2
C00000H
ROS1
(256K Byte)
C40000H
ROS2
(Not used)
CA0000H
D00000H
ROS3
NOT USE
EFFFFFH
Fig. 5-3
RAM image area
Internal I/O area
External I/O area
(0 page)

Advertisement

Table of Contents
loading

Table of Contents