Protech Systems PROX-1750 User Manual page 93

Appendix B Technical Summary
Memory Decode Ranges From Processor Perspective :
Memory Range
0000 0000h-000D FFFFh
0010 0000-TOM (Top of
Memory)
000E 0000h-000F FFFFh
FEC0 0000h-FEC0 0100h
FFC0 0000h-FFC7 FFFFh
FF80 0000h-FF87 FFFFh
FFC8 0000h-FFCF FFFFh
FF88 0000h-FF8F FFFFh
FFD0 0000h-FFD7 FFFFh
FF90 0000h-FF97 FFFFh
FFD8 0000h-FFDF FFFFh
FF98 0000h-FF9F FFFFh
FFE0 0000h-FFE7 FFFFh
FFA0 0000h-FFA7 FFFFh
FFE8 0000h-FFEF FFFFh
FFA8 0000h-FFAF FFFFh
FFF0 0000h-FFF7 FFFFh
FFB0 0000h-FFB7 FFFFh
FFF8 0000h-FFFF FFFFh
FFB8 0000h-FFBF FFFFh
FF70 0000h-FF7F FFFFh
FF30 0000h-FF3F FFFFh
FF60 0000h-FF6F FFFFh
FF20 0000h-FF2F FFFFh
FF50 0000h-FF5F FFFFh
FF10 0000h-FF1F FFFFh
FF40 0000h-FF4F FFFFh
FF00 0000h-FF0F FFFFh
Anywhere in 4GB range
All Other
Page: B-8
Target
Main Memory
FWH
I/O APIC inside ICH2
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
FWH
D110 LAN Controller Enable via BAR in Device
PCI
Prox-1750G1/G2 USER
Dependency/Comments
TOM registers in Host Controller
Bit 7 in FWH Decode Enable
Register is set
Bit 0 in FWH Decode Enable
Register
Bit 1 in FWH Decode Enable
Register
Bit 2 in FWH Decode Enable
Register is set
Bit 3 in FWH Decode Enable
Register is set
Bit 4 in FWH Decode Enable
Register is set
Bit 5 in FWH Decode Enable
Register is set
Bit 6 in FWH Decode Enable
Register is set
Always Enabled.
The top two 64K blocks of this
range can be swapped as
described in Section 6.4.1.
Bit 3 in FWH Decode Enable 2
Register is set
Bit 2 in FWH Decode Enable 2
Register is set
Bit 1 in FWH Decode Enable 2
Register is set
Bit 0 in FWH Decode Enable 2
Register is set
29:Function 0 (D110 LAN
Controller)
None
'
S MANUAL