Chipset; Intel 7500 Chipset I/O Hub (Ioh); Ioh Quickpath Interconnect (Qpi); Pci Express Generation 2 - Dell PowerEdge R910 Technical Manual

Dell

8 Chipset

The Dell™ PowerEdge™ R910 system-board incorporates the Intel
interfacing. The Intel 7500 chipset is designed to support the Intel Xeon
product family, and the Intel Xeon processor 7500 series, QPI interconnect, DDR3 memory technology,
and PCI Express Generation 2. The Intel 7500 chipset consists of the EX IOH, Intel
Memory Buffer, and the ICH10 South Bridge.

8.1 Intel 7500 Chipset I/O Hub (IOH)

The R910 motherboard incorporates dual Intel 7500 chipset IOH to provide a link between the four
Intel Xeon processor 7500 series sockets and the I/O components. The main components of the IOH
consist of two full-width QPI links (one to each processor), 72 lanes of PCIe Gen2, and a x4 DMI link
to connect directly to the ICH10 South Bridge.

8.2 IOH QuickPath Interconnect (QPI)

The QuickPath Architecture consists of serial point-to-point interconnects for the processors and the
IOH. The PowerEdge R910 has a total of four QuickPath Interconnect (QPI) links including one link
connecting the processors and links connecting both processors with the IOH and links connecting
both IOHs. Each link consists of 20 lanes (full-width) in each direction with a link speed of 6.4 GT/s.
An additional lane is reserved for a forwarded clock. Data is sent over the QPI links as packets.
The QuickPath Architecture features four layers. The physical layer consists of the actual connection
between components, and supports polarity inversion and lane reversal for optimizing component
placement and routing. The link layer is responsible for flow control and the reliable transmission of
data. The routing layer is responsible for the routing of QPI data packets. The protocol layer is
responsible for high-level protocol communications, including the implementation of a MESIF (modify,
exclusive, shared, invalid, forward) cache coherence protocol.

8.3 PCI Express Generation 2

PCI Express Generation 2 (PCIe Gen2) is a serial point to point interconnects for I/O devices. PCIe
Gen2 doubles the signaling bit rate of each lane from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2
ports is backwards compatible with Gen1 transfer rates.

8.4 Direct Media Interface (DMI)

The DMI (previously called the Enterprise Southbridge Interface) connects the Boxboro‐EX Legacy IOH
with the Intel I/O Controller Hub (ICH). The DMI is equivalent to a x4 PCIe Gen1 link with a transfer
rate of 1 GB/s in each direction.

8.5 Intel I/O Controller Hub 10 (ICH10)

ICH10 is a highly integrated I/O controller, supporting the following functions:

Six x1 PCIe Gen1 ports, with the capability of combining ports 1-4 as a x4 link

Used on PowerEdge R910 for slot 5

PCI Bus 32-bit Interface Rev 2.3 running at 33 MT/s

Up to six Serial ATA (SATA) ports with transfer rates up to 300 MB/s

R910 features one SATA port for optional internal optical drive

Six UHCI and two EHCI (High-Speed 2.0) USB host controllers, with up to twelve USB ports
(R910 has four external USB ports and one internal ports dedicated for IDSM and embedded
storage)

Power management interface (ACPI 3.0b compliant)
Dell PowerEdge R910 Technical Guide
®
7500 chipset for I/O and processor
®
E7-4800 and E7-8800
®
7500 Scalable
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