Memory; Overview; Slots And Risers; Key Features Of The Memory Subsystem - Dell PowerEdge R910 Technical Manual

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7 Memory

7.1 Overview

The Dell™ PowerEdge™ R910 uses DDR3 memory providing a high-performance, high-speed memory
interface capable of low latency response and high throughput. The R910 supports Registered ECC
DDR3 DIMMs (RDIMM).
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R910 uses the Intel Xeon
of those memory controllers then has two Scalable Memory Interconnect (SMI) channels that connect
to the memory buffer. The R910 has both the SMI channels from each controller routed to the
memory riser with two memory buffers connected.
The SMI channels from each controller operate in lockstep (the DIMMs need to be populated in
matched pairs behind lockstep channel). Each memory buffer has two DDR3 channels that can
support up to two DIMMs per channel.
The DDR3 memory interface consists of 16 memory buffers, each of which has two DDR3 memory
channels. Each channel supports up to two RDIMMs for single/dual/quad rank. By limiting to two
DIMMs per DDR channel, the system can support DIMMs at 1333 MT/s.
The R910 memory interface supports memory demand and patrol scrubbing, single-bit correction and
multi-bit error detection. Correction of a x4 or x8 device failure (chip kill) is supported with SDDC.
The following properties/rules apply to R910:

DIMMs must be populated in matched pairs for each processor (A1/A2, A3/A4). Single DIMM
operation is not supported.

If DIMMs of different speeds are mixed, all channels will operate at the fastest common
frequency. Note that R910 only supports DDR3 1333 MT/s modules.

Memory mirroring and sparing configurations will be supported as follows:
o Memory sparing will be allowed on configurations with >= 64GB populated
o Memory mirroring will be enabled on configurations with >=64GB populated

The first DIMM slot in each channel is color-coded with white ejection tabs for ease of
installation.

In the case of mixed-rank population, populate the DIMM with the highest number of ranks
first (in sockets with white ejection tabs)

DIMM sockets are placed 0.450" (11.43 mm) apart, center-to-center in order to provide
enough space for sufficient airflow to cool stacked DIMMs. DIMMs must be installed in each
channel starting with the DIMM farthest from the processor (DIMM 1). Population order is
identified by silkscreen and a label. The order is dependent on the memory configuration
used.

7.2 Slots and Risers

R910 has 8 memory risers; each memory riser has 8 DIMM slots. So there are a total of 64 DIMMs. See
the Dell PowerEdge R910 Systems Hardware Owner's Manual on
detailed information.

7.3 Key Features of the Memory Subsystem

Registered (RDIMM) ECC DDR3 technology:

Each channel carries 64 data and 8 ECC bits

Support for up to 2 TB of memory (with sixty-four 32 GB RDIMMs)

Support for 1333 MT/s single, dual, and quad rank DIMMs

Support ODT (On Die Termination)
Dell PowerEdge R910 Technical Guide
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processor 7500 series that has two integrated memory controllers. Each
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