Manageability - Intel S2600CO Family Technical Product Specification

Intel® Server Board S2600CO Family TPS
Open Source Compliance = Binary Driver (includes Partial Source files) or Open Source

using MDRAID layer in Linux.
OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL*, SLES, other Linux*

variants using partial source builds.
Utilities = Windows* GUI and CLI, Linux GUI and CLI, DOS CLI, and EFI CLI

3.3.3.2 Intel Rapid Storage Technology (RSTe)
®
Features of the embedded software RAID option Intel
include the following:
Software RAID with system providing memory and CPU utilization

Supported RAID Levels – 0,1,5,10

o 4 Port SATA RAID 5 available standard (no option key required)
o 8 Port SATA RAID 5 support provided with appropriate Intel
Upgrade Key
o No SAS RAID 5 support
Maximum drive support = 32 (in arrays with 8 port SAS), 16 (in arrays with 4 port SAS),

128 (JBOD)
Open Source Compliance = Yes (uses MDRAID)

OS Support = Windows 7*, Windows 2008*, Windows 2003*, RHEL* 6.2 and later,

SLES* 11 w/SP2 and later, VMWare 5.x.
Utilities = Windows* GUI and CLI, Linux CLI, DOS CLI, and EFI CLI

Uses Matrix Storage Manager for Windows

MDRAID supported in Linux (Does not require a driver)

Note: No boot drive support to targets attached through SAS expander card
3.3.4

Manageability

The chipset integrates several functions designed to manage the system and lower the total
cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller.
TCO Timer. The chipset's integrated programmable TCO timer is used to detect system

locks. The first expiration of the timer generates an SMI# that the system can use to
recover from a software lock. The second expiration of the timer causes a system reset
to recover from a hardware lock.
Processor Present Indicator. The chipset looks for the processor to fetch the first

instruction after reset. If the processor does not fetch the first instruction, the chipset will
reboot the system.
ECC Error Reporting. When detecting an ECC error, the host controller has the ability

to send one of several messages to the chipset. The host controller can instruct the
chipset to generate an SMI#, NMI, SERR#, or TCO interrupt.
Function Disable. The chipset provides the ability to disable the following integrated

functions: LAN, USB, LPC, SATA, PCI Express or SMBus. Once disabled, these
Revision 1.0
®
Rapid Storage Technology (RSTe)
Intel order number G42278-002
Functional Architecture Overview
®
RAID C600
37