Intel S2600CO Family Technical Product Specification page 37

Functional Architecture Overview
Note: Some server operating systems do not display the total physical memory installed. What
is displayed is the amount of physical memory minus the approximate memory space used by
system BIOS components. These BIOS components include, but are not limited to:
ACPI (may vary depending on the number of PCI devices detected in the system)

ACPI NVS table

Processor microcode

Memory Mapped I/O (MMIO)

Manageability Engine (ME)

BIOS flash(

3.2.2.4 Integrated Memory Controller Operating Modes
3.2.2.4.1 Independent Channel Mode
In non-ECC (Error Correction Code) and x4 Single Device Data Correction (SDDC)
configuration, each channel is running independently (nonlock-step), that is, each cache-line
from memory is provided by a channel. To deliver the 64-byte cache-line of data, each channel
is bursting eight 8-byte chunks, Back to back data transfer in the same direction and within the
same rank can be sent back-to-back without any dead-cycle. The independent channel mode is
the recommended method to deliver most efficient power and bandwidth as long as the x8
SDDC is not required.
3.2.2.4.2 Lockstep Channel Mode
In Lockstep Channel Mode the cache-line is split across channels. This is done to support
Single Device Data Correction (SDDC) for DRAM devices with 8-bit wide data ports. Also, the
same address is used on both channels, such that an address error on any channel is
detectable by bad ECC. The IMC module always accumulates 32-bytes before forwarding data
so there is no latency benefit for disabling ECC.
Lockstep channels must be populated identically. That is, each DIMM in one channel must have
a corresponding DIMM of identical organization (number ranks, number banks, number rows,
and number columns). DIMMs may be of different speed grades, but the IMC module will be
configured to operate all DIMMs according to the slowest parameters present by the Memory
Reference Code (MRC).
Channel 0 and channel 1 can be in lockstep. Channel 2 and channel 3 can be in lockstep.
Performance in lockstep mode cannot be as high as with independent channels. The burst
length for DDR3 DIMMs is eight which is shared between two channels that are in lockstep
mode. Each channel of the pair provides 32 bytes to produce the 64-byte cache-line. DRAMs on
independent channels are configured to deliver a burst length of eight. The maximum read
bandwidth for a given rank is half of peak. There is another drawback in using lockstep mode,
i.e. higher power consumption since the total activation power is about twice of the independent
channel operation if comparing to same type of DIMMs.
3.2.2.4.3 Mirror Mode
Memory mirroring mode is the mechanism by which a component of memory is mirrored. In
mirrored mode, when a write is performed to one copy, a write is generated to the target
location as well. This guarantees that the target is always updated with the latest data from the
main copy. The IMC module supports mirroring across the corresponding mirroring channel
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Intel order number G42278-002
Intel® Server Board S2600CO Family TPS
Revision 1.0