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Fujitsu MHS2030AT - 2.5" Notebook 30GB Drive Product Manual

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C141-E171-03EN
MHS2060AT, MHS2040AT
MHS2030AT, MHS2020AT
DISK DRIVES
PRODUCT MANUAL

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Summary of Contents for Fujitsu MHS2030AT - 2.5" Notebook 30GB Drive

  • Page 1 C141-E171-03EN MHS2060AT, MHS2040AT MHS2030AT, MHS2020AT DISK DRIVES PRODUCT MANUAL...
  • Page 2 “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully. FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.

  • Page 3: Revision History

    Revision History (1/1) Revised section (*1) Edition Date Details (Added/Deleted/Altered) 2002-07-12 2002-07-31 2002-09-20 *1 Section(s) with asterisk (*) refer to the previous edition when those were deleted. C141-E171-03EN...
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  • Page 5 Preface This manual describes the MHS Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface. This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

  • Page 6: Operating Environment

    Preface Conventions for Alert Messages This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word. The following are the alert signals and their meanings: This indicates a hazardous situation could result in minor or moderate personal injury if the user does...
  • Page 7 “Disk drive defects” refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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  • Page 9: Important Alert Items

    Important Alert Items Important Alert Messages The important alert messages in this manual are as follows: A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.
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  • Page 11: Manual Organization

    Manual Organization MHS2060AT, MHS2040AT • Device Overview MHS2030AT, MHS2020AT • Device Configuration • Installation Conditions DISK DRIVES • Theory of Device Operation PRODUCT MANUAL • Interface (C141-E171) • Operations <This manual> MHS2060AT, MHS2040AT • Maintenance and Diagnosis MHS2030AT, MHS2020AT • Removal and Replacement Procedure DISK DRIVES MAINTENANCE MANUAL (C141-F059)
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  • Page 13: Table Of Contents

    Contents Device Overview ....................1-1 Features ....................1-2 1.1.1 Functions and performance ..............1-2 1.1.2 Adaptability...................1-2 1.1.3 Interface....................1-3 Device Specifications................1-4 1.2.1 Specifications summary ................1-4 1.2.2 Model and product number ..............1-5 Power Requirements ................1-5 Environmental Specifications ..............1-8 Acoustic Noise ..................1-9 Shock and Vibration................1-9 Reliability....................1-10 Error Rate ....................1-11 Media Defects ..................1-11...
  • Page 14 Contents CHAPTER 3 Installation Conditions ............. 3-1 Dimensions ....................3-2 Mounting ....................3-3 Cable Connections...................3-9 3.3.1 Device connector ...................3-9 3.3.2 Cable connector specifications............3-10 3.3.3 Device connection ................3-10 3.3.4 Power supply connector (CN1) ............3-11 Jumper Settings ..................3-11 3.4.1 Location of setting jumpers..............3-11 3.4.2 Factory default setting.................3-12 3.4.3 Master drive-slave drive setting ............3-12...
  • Page 15 Contents 4.6.1 Read/write preamplifier (HDIC) ............4-10 4.6.2 Write circuit ..................4-10 4.6.3 Read circuit ..................4-12 4.6.4 Digital PLL circuit ................4-13 Servo Control ..................4-14 4.7.1 Servo control circuit................4-14 4.7.2 Data-surface servo format ..............4-17 4.7.3 Servo frame format................4-19 4.7.4 Actuator motor control................4-20 4.7.5 Spindle motor control................4-21 CHAPTER 5 Interface ..................
  • Page 16 Contents 5.5.3 Ultra DMA data in commands ............5-116 5.5.3.1 Initiating an Ultra DMA data in burst ..........5-116 5.5.3.2 The data in transfer................5-117 5.5.3.3 Pausing an Ultra DMA data in burst ..........5-117 5.5.3.4 Terminating an Ultra DMA data in burst ........5-118 5.5.4 Ultra DMA data out commands ............5-121 5.5.4.1 Initiating an Ultra DMA data out burst ...........5-121...
  • Page 17 Contents 6.1.4 Response to diagnostic command ............6-6 Power Save....................6-7 6.2.1 Power save mode...................6-7 6.2.2 Power commands ..................6-9 Defect Processing..................6-9 6.3.1 Spare area ....................6-9 6.3.2 Alternating processing for defective sectors........6-10 Read-ahead Cache .................6-12 6.4.1 Data buffer structure ................6-12 6.4.2 Caching operation ................6-12 6.4.3 Using the read segment buffer ............6-15 6.4.3.1 Miss-hit (no hit) ................6-15...
  • Page 18 Contents Illustrations Figures Figure 1.1 Negative voltage at +5V when power is turned off ......1-6 Figure 1.2 Current fluctuation (Typ.) at +5V when power is turned on .....1-8 Figure 2.1 Disk drive outerview ................2-2 Figure 2.2 Configuration of disk media heads.............2-3 Figure 2.3 1 drive system configuration ..............2-4 Figure 2.4...
  • Page 19 Contents Figure 5.1 Interface signals..................5-2 Figure 5.2 Execution example of READ MULTIPLE command .....5-21 Figure 5.3 Read Sector(s) command protocol ..........5-107 Figure 5.4 Protocol for command abort ............5-108 Figure 5.5 WRITE SECTOR(S) command protocol........5-110 Figure 5.6 Protocol for the command execution without data transfer ...5-111 Figure 5.7 Normal DMA data transfer ............5-114 Figure 5.8...
  • Page 20 Contents Tables Table 1.1 Specifications ..................1-4 Table 1.2 Model names and product numbers............1-5 Table 1.3 Current and power dissipation ............1-7 Table 1.4 Environmental specifications .............1-8 Table 1.5 Acoustic noise specification...............1-9 Table 1.6 Shock and vibration specification ............1-9 Table 3.1 Surface temperature measurement points and standard values..3-6 Table 3.2 Cable connector specifications............3-10 Table 5.1...

  • Page 21: Device Overview

    CHAPTER 1 Device Overview Features Device Specifications Power Requirements Environmental Specifications Acoustic Noise Shock and Vibration Reliability Error Rate Media Defects 1.10 Load/Unload Function 1.11 Advanced Power Management Overview and features are described in this chapter, and specifications and power requirement are described.

  • Page 22: Features

    Device Overview 1.1 Features 1.1.1 Functions and performance The following features of the MHS Series are described. (1) Compact The MHS Series has 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch). (2) Large capacity The disk drive can record up to 30 GB (formatted) on one disk using the 48/50 RLL recording method and 30 recording zone technology.

  • Page 23: Interface

    1.1 Features 1.1.3 Interface (1) Connection to ATA interface The MHS-series disk drives have built-in controllers compatible with the ATA interface. (2) 2 MB data buffer The disk drives (the MHS Series) use a 2 MB data buffer to transfer data between the host and the disk media.

  • Page 24: Device Specifications

    Device Overview 1.2 Device Specifications 1.2.1 Specifications summary Table 1.1 shows the specifications of the disk drives (MHS Series). Table 1.1 Specifications (1/2) MHS2060AT MHS2040AT MHS2030AT MHS2020AT Format Capacity (*1) 60 GB 40 GB 30 GB 20 GB Number of Heads Number of Cylinders (User) 47104 47104...

  • Page 25: Model And Product Number

    1.3 Power Requirements Table 1.1 lists the formatted capacity, number of logical cylinders, number of heads, and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host. Table 1.1 Specifications (2/2) Model Capacity (*1) No.

  • Page 26: Figure 1.1 Negative Voltage At +5V When Power Is Turned Off

    Device Overview (3) A negative voltage like the bottom figure isn't to occur at +5V when power is turned off and, a thing with no ringing. Permissible level: 0.2V Time [ms] Figure 1.1 Negative voltage at +5V when power is turned off C141-E171-03EN...

  • Page 27: Table 1.3 Current And Power Dissipation

    1.3 Power Requirements (4) Current Requirements and Power Dissipation Table 1.3 lists the current and power dissipation (typical). Table 1.3 Current and power dissipation Typical RMS Current Typical Power (*3) MHS Series MHS Series Spin up (*1) 0.9 A 4.5 W Idle 130 mA 0.65 W...

  • Page 28: Environmental Specifications

    Device Overview Figure 1.2 Current fluctuation (Typ.) at +5V when power is turned on (6) Power on/off sequence The voltage detector circuits (the MHS Series) monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

  • Page 29: Acoustic Noise

    1.5 Acoustic Noise 1.5 Acoustic Noise Table 1.5 lists the acoustic noise specification. Table 1.5 Acoustic noise specification Item Specification Sound Pressure • Idle mode (DRIVE READY) 24 dBA typical at 0.3 m Note: Measure the noise from the cover top surface. 1.6 Shock and Vibration Table 1.6 lists the shock and vibration specification.

  • Page 30: Reliability

    Device Overview 1.7 Reliability (1) Mean time between failures (MTBF) Conditions of 300,000 h Power-on time 250H/month or less 3000H/years or less Operating time 20% or less of power-on time Environment 5 to 55°C/8 to 90% But humidity bulb temperature 29°C or less MTBF is defined as follows: Total operation time in all fields...

  • Page 31: Error Rate

    1.8 Error Rate 1.8 Error Rate Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media. (1) Unrecoverable read error Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading...

  • Page 32: Advanced Power Management

    Device Overview Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.
  • Page 33 1.8 Error Rate Active Idle: The head is in a position of extreme inner in disk medium. (VCM Lock) Low power Idle: The head is unloaded from disk. (VCM Unload) The spindle motor rotates. Standby: The spindle motor stops. Active Idle Low Power Idle Standby APM Mode...
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  • Page 35: Chapter 2 Device Configuration

    CHAPTER 2 Device Configuration Device Configuration System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate. C141-E171-03EN...

  • Page 36: Device Configuration

    Device Configuration 2.1 Device Configuration Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter. MHS Series Figure 2.1 Disk drive outerview (1) Disk...

  • Page 37: Figure 2.2 Configuration Of Disk Media Heads

    2.1 Device Configuration Head Head Head MHS2060AT MHS2040AT MHS2030AT MHS2020AT Head 0 to Head 2 is mounted or Head 1 to Head 3 is mounted or Head 0 to Head 3 is mounted Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor.

  • Page 38: System Configuration

    Device Configuration 2.2 System Configuration 2.2.1 ATA interface Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 44pin PC AT interface connector and supports PIO mode 4 transfer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s).
  • Page 39 2.2 System Configuration IMPORTANT HA (host adaptor) consists of address decoder, driver, and receiver. ATA is an abbreviation of “AT attachment”. The disk drive is conformed to the ATA-6 interface. At high speed data transfer (PIO mode 4 or DMA mode 2 U-DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability.
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  • Page 41: Chapter 3 Installation Conditions

    CHAPTER 3 Installation Conditions Dimensions Mounting Cable Connections Jumper Settings This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives. For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide.

  • Page 42: Dimensions

    Installation Conditions 3.1 Dimensions Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm. Figure 3.1 Dimensions C141-E171-03EN...

  • Page 43: Mounting

    3.2 Mounting 3.2 Mounting For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE(C141-E144-01EN)." (1) Orientation Figure 3.2 illustrates the allowable orientations for the disk drive. gravity (a) Horizontal –1 (b) Horizontal –1 gravity (c) Vertical –1 (d) Vertical –2 gravity (f) Vertical –4...

  • Page 44: Figure 3.3 Mounting Frame Structure

    Installation Conditions (2) Frame The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to SG. IMPORTANT Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3. The tightening torque must be 0.49N·m(5kgf·cm).

  • Page 45: Figure 3.4 Location Of Breather

    3.2 Mounting IMPORTANT Because of breather hole mounted to the HDD, do not allow this to close during mounting. Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around 2.4 to block.

  • Page 46: Figure 3.5 Surface Temperature Measurement Points

    Installation Conditions (4) Ambient temperature The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface temperature from exceeding 60 C.

  • Page 47: Figure 3.6 Service Area

    3.2 Mounting (5) Service area Figure 3.6 shows how the drive must be accessed (service areas) during and after installation. Mounting screw hole Cable connection Mounting screw hole Figure 3.6 Service area Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers.

  • Page 48: Figure 3.7 Handling Cautions

    Installation Conditions General notes ESD mat Shock absorbing mat Wrist strap Use the Wrist strap. Place the shock absorbing mat on the operation table, and place ESD mat on it. Do not hit HDD each other. Do not stack when carrying. Do not place HDD vertically Do not drop.

  • Page 49: Cable Connections

    3.3 Cable Connections 3.3 Cable Connections 3.3.1 Device connector The disk drive has the connectors and terminals listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals. Connector, setting pins Figure 3.8 Connector locations C141-E171-03EN...

  • Page 50: Cable Connector Specifications

    Installation Conditions 3.3.2 Cable connector specifications Table 3.2 lists the recommended specifications for the cable connectors. Table 3.2 Cable connector specifications Name Model Manufacturer ATA interface and power Cable socket 89361-144 supply cable (44-pin type) (44-pin type) IMPORTANT For the host interface cable, use a ribbon cable. A twisted cable or a cable with wires that have become separated from the ribbon may cause crosstalk between signal lines.

  • Page 51: Power Supply Connector (Cn1)

    3.4 Jumper Settings 3.3.4 Power supply connector (CN1) Figure 3.10 shows the pin assignment of the power supply connector (CN1). Figure 3.10 Power supply connector pins (CN1) 3.4 Jumper Settings 3.4.1 Location of setting jumpers Figure 3.11 shows the location of the jumpers to select drive configuration and functions.

  • Page 52: Factory Default Setting

    Installation Conditions 3.4.2 Factory default setting Figure 3.12 shows the default setting position at the factory. Open Figure 3.12 Factory default setting 3.4.3 Master drive-slave drive setting Master drive (disk drive #0) or slave drive (disk drive #1) is selected. Open Short Open...

  • Page 53: Csel Setting

    3.4 Jumper Settings 3.4.4 CSEL setting Figure 3.14 shows the cable select (CSEL) setting. Open Short Note: The CSEL setting is not depended on setting between pins Band D. Figure 3.14 CSEL setting Figure 3.15 and 3.16 show examples of cable selection using unique interface cables.

  • Page 54: Power Up In Standby Setting

    Installation Conditions drive drive Figure 3.16 Example (2) of Cable Select 3.4.5 Power Up in Standby setting When pin C is grounded, the drive does not spin up at power on. 3-14 C141-E171-03EN...

  • Page 55: Chapter 4 Theory Of Device Operation

    CHAPTER 4 Theory of Device Operation Outline Subassemblies Circuit Configuration Power-on Sequence Self-calibration Read/write Circuit Servo Control This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

  • Page 56: Outline

    Theory of Device Operation 4.1 Outline This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method. 4.2 Subassemblies The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

  • Page 57: Spindle

    4.2 Subassemblies Head Head Head MHS2060AT MHS2040AT MHS2030AT MHS2020AT Head 0 to Head 2 is mounted or Head 1 to Head 3 is mounted or Head 0 to Head 3 is mounted Figure 4.1 Head structure 4.2.3 Spindle The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 4,200 rpm 1%.

  • Page 58: Circuit Configuration

    Theory of Device Operation 4.3 Circuit Configuration Figure 4.2 shows the power supply configuration of the disk drive, and Figure 4.3 shows the disk drive circuit configuration. (1) Read/write circuit The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel (RDC).

  • Page 59: Figure 4.2 Power Supply Configuration

    4.3 Circuit Configuration 5.0V 1.8-V S-DRAM HDIC F-ROM generator - 3.0V 3.3V circuit 2.0V & Figure 4.2 Power Supply Configuration C141-E171-03EN...

  • Page 60: Figure 4.3 Circuit Configuration

    Theory of Device Operation Figure 4.3 Circuit Configuration C141-E171-03EN...

  • Page 61: Power-On Sequence

    4.4 Power-on Sequence 4.4 Power-on Sequence Figure 4.4 describes the operation sequence of the disk drive at power-on. The outline is described below. a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

  • Page 62: Self-Calibration

    Theory of Device Operation Power-on Start Self-diagnosis 1 - MPU bus test - Internal register write/read test - Work RAM write/read test The spindle motor starts. Self-diagnosis 2 - Data buffer write/read Initial on-track and read test out of system information Confirming spindle motor Execute self-calibration speed...

  • Page 63: Execution Timing Of Self-Calibration

    4.5 Self-calibration The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varying by the cylinder, the disk is divided into 16 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration.

  • Page 64: Command Processing During Self-Calibration

    Theory of Device Operation 4.5.3 Command processing during self-calibration This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 72 ms. When the error rate of data reading, writing, or seeking becomes lower than the specified value, self-calibration is performed to maintain disk drive stability.

  • Page 65: Figure 4.5 Read/Write Circuit Block Diagram

    4.6 Read/write Circuit HDIC WDX/WDY RDX/RDY Serial I/O Write PreCompen- Amplifier sation Registers Digital Programmable Filter Flash Digitizer MEEPR ServoPulse Viterbi Detector Detect 16/17 ENDEC Position A/B/C/D (to reg) WTGATE REFCLK RDGATE DATA RWCLK SRV_CLK SRV_OUT[1:0] [7:0] Figure 4.5 Read/write circuit block diagram C141-E171-03EN 4-11...

  • Page 66: Read Circuit

    Theory of Device Operation 4.6.3 Read circuit The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

  • Page 67: Digital Pll Circuit

    4.6 Read/write Circuit (3) FIR circuit This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform. (4) A/D converter circuit This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.

  • Page 68: Servo Control

    Theory of Device Operation 4.7 Servo Control The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.
  • Page 69 4.7 Servo Control The major internal operations are listed below. Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is applied. b. Move head to reference cylinder Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).
  • Page 70 Theory of Device Operation (2) Servo burst capture circuit The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. From the servo area on the data area surface, via the data head, the burst signal of SERVO A, SERVO B, SERVO C, and SERVO D is output as shown in Figure 4.9 in subsequent to the servo mark, gray code that indicates the cylinder position, and index information.

  • Page 71: Data-Surface Servo Format

    4.7 Servo Control 4.7.2 Data-surface servo format Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.8 are described below. (1) Inner guard band This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.

  • Page 72: Figure 4.8 Physical Sector Servo Configuration On Disk Surface

    Theory of Device Operation Servo frame (140 servo frames per revolution) Data area expand CYLn CYLn – 1 (n: even number) CYLn + 1 Diameter direction W/R Recovery W/R Recovery W/R Recovery Servo Mark Servo Mark Servo Mark Gray Code Gray Code Gray Code Erase...

  • Page 73: Servo Frame Format

    4.7 Servo Control 4.7.3 Servo frame format As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction. The servo frame consists of 6 blocks;...

  • Page 74: Actuator Motor Control

    Theory of Device Operation (1) Write/read recovery This area is used to absorb the write/read transient and to stabilize the AGC. (2) Servo mark This area generates a timing for demodulating the gray code and position- demodulating the servo A to D by detecting the servo mark. (3) Gray code (including index bit) This area is used as cylinder address.

  • Page 75: Spindle Motor Control

    (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.
  • Page 76 Theory of Device Operation d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.

  • Page 77: Chapter 5 Interface

    CHAPTER 5 Interface Physical Interface Logical Interface Host Commands Command Protocol Ultra DMA Feature Set Timing This chapter gives details about the interface, and the interface commands and timings. C141-E171-03EN...

  • Page 78: Physical Interface

    Interface 5.1 Physical Interface 5.1.1 Interface signals Figure 5.1 shows the interface signals. Host DATA 0-15: DATA BUS DMACK-: DMA ACKNOWLEDGE DMARQ: DMA REQUEST INTRO: INTERRUPT REQUEST DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS DIOR-:I/O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE DURING ULTRA DMA DATA OUT BURST PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER...

  • Page 79: Signal Assignment On The Connector

    5.1 Physical Interface 5.1.2 Signal assignment on the connector Table 5.1 shows the signal assignment on the interface connector. Table 5.1 Signal assignment on the interface connector Pin No. Signal Pin No. Signal MSTR MSTR/ENCSEL PUS- ENCSEL (KEY) (KEY) RESET– DATA7 DATA8 DATA6...
  • Page 80 Interface [signal] [I/O] [Description] ENCSEL This signal is used to set master/slave using the CSEL signal (pin 28). Pins B and D Open: Sets master/slave using the CSEL signal is disabled. Short: Sets master/slave using the CSEL signal is enabled. MSTR- MSTR, I, Master/slave setting Pin A, B, C, D open: Master setting...
  • Page 81 5.1 Physical Interface [signal] [I/O] [Description] CS0- Chip select signal decoded from the host address bus. This signal is used by the host to select the command block registers. CS1- Chip select signal decoded from the host address bus. This signal is used by the host to select the control block registers.

  • Page 82: Logical Interface

    Interface [signal] [I/O] [Description] DMARQ This signal is used for DMA transfer between the host system and the device. The device asserts this signal when the device completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing). The direction of data transfer is controlled by the DIOR and DIOW signals.

  • Page 83: I/O Registers

    5.2 Logical Interface 5.2.1 I/O registers Communication between the host system and the device is done through input- output (I/O) registers of the device. These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2. shows the coding address and the function of I/O registers.

  • Page 84: Command Block Registers

    Interface Device/Head, Cylinder High, Cylinder Low, Sector Number registers indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively. If the LBA mode is specified with 48-bit address information, the Cylinder High, Cylinder Low, Sector Number registers are set twice.
  • Page 85 5.2 Logical Interface - Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution. - Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred. [Diagnostic code] X’01’: No Error Detected.
  • Page 86 Interface (5) Sector Number register (X’1F3’) The contents of this register indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command. Under the LBA mode, this register indicates LBA bits 7 to 0.
  • Page 87 5.2 Logical Interface (8) Device/Head register (X’1F6’) The contents of this register indicate the device and the head number. When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register defines “the number of heads minus 1” (a maximum head No.). Bit 7 Bit 6 Bit 5...
  • Page 88 Interface - Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1).When BSY bit is 1, the host system should not write the command block registers.

  • Page 89: Control Block Registers

    5.2 Logical Interface - Bit 1: Always 0. - Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error. (10) Command register (X’1F7’) The Command register contains a command code being sent to the device.

  • Page 90: Host Commands

    Interface (2) Device Control register (X’3F6’) The Device Control register contains device interrupt and software reset. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRST nIEN - Bit 7: HOB is the selector bit that selects higher-order information or lower- order information of the EXT system command.

  • Page 91: Table 5.3 Command Code And Parameters

    5.3 Host Commands Table 5.3 Command code and parameters (1 of 3) Command code (Bit) Parameters used Command name FR SC SN CY DH READ SECTOR(S) READ MULTIPLE READ DMA READ VERIFY SECTOR(S) WRITE MULTIPLE WRITE DMA WRITE VERIFY WRITE SECTOR(S) RECALIBRATE SEEK INITIALIZE DEVICE PARAMETERS 1...
  • Page 92 Interface Table 5.3 Command code and parameters (2 of 3) Command code (Bit) Parameters used Command name FR SC SN CY DH IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK...
  • Page 93 5.3 Host Commands Table 5.3 Command code and parameters (3 of 3) Command code (Bit) Parameters used Command name FR SC SN CY DH DEVICE CONFIGURATION IDENTIFY DEVICE CONFIGURATION SET READ NATIVE MAX ADDRESS SET MAX ADDRESS EXT FLUSH CACHE EXT WRITE DMA EXT READ DMA EXT WRITE MULTIPLE EXT...

  • Page 94: Command Descriptions

    Interface The command is addressed to the master device, but both the master device and the slave device execute it. Do not care 5.3.2 Command descriptions The contents of the I/O registers to be necessary for issuing a command and the example indication of the I/O registers at command completion are shown as following in this subsection.
  • Page 95 5.3 Host Commands CM: Command register FR: Features register DH: Device/Head register ST: Status register CH: Cylinder High register ER: Error register CL: Cylinder Low register L: LBA (logical block address) setting bit SN: Sector Number register DV: Device address. bit SC: Sector Count register x, xx: Do not care (no necessary to set) Note:...
  • Page 96 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) (R: Retry) At command completion (I/O registers contents to be read)
  • Page 97 5.3 Host Commands final partial block is transferred. The number of sectors in the partial block to be transferred is n where n = remainder of (“number of sectors”/”block count”). If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is executed or when the READ MULTIPLE command is disabled, the device rejects the READ MULTIPLE command with an ABORTED COMMAND error.
  • Page 98 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) End head No. / LBA [MSB] (CH) End cylinder No. [MSB] / LBA (CL) End cylinder No. [LSB] / LBA (SN) End sector No. / LBA [LSB] (*1) (SC) (ER)
  • Page 99 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 100 Interface At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read) (ST)
  • Page 101 5.3 Host Commands If an error occurs during multiple sector write operation, the write operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector where the error occurred.
  • Page 102 Interface (6) WRITE MULTIPLE (X’C5’) This command is similar to the WRITE SECTOR(S) command. The device does not generate interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which contains the number of sectors for which the number is defined by the SET MULTIPLE MODE command.
  • Page 103 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 104 Interface A host system can select the following transfer mode using the SET FEATURES command. Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No.
  • Page 105 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Start head No. / LBA [MSB] (CH) Start cylinder No. [MSB] / LBA (CL) Start cylinder No. [LSB] / LBA (SN) Start sector No. / LBA [LSB] (SC) Transfer sector count (FR) At command completion (I/O registers contents to be read)
  • Page 106 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Note: Also executable in LBA mode. (10) SEEK (X’7x’, x : X’0’...
  • Page 107 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) Head No. / LBA [MSB] (CH) Cylinder No. [MSB] / LBA (CL) Cylinder No. [LSB] / LBA (SN) Sector No. / LBA [LSB] (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH)
  • Page 108 Interface At command issuance (I/O registers setting contents) (CM) (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) Max. head No. (CH) (CL) (SN) (SC) Number of sectors/track (ER)
  • Page 109 5.3 Host Commands (13) IDENTIFY DEVICE DMA (X’EE’) When this command is not used to transfer data to the host in DMA mode, this command functions in the same way as the Identify Device command. At command issuance (I/O registers setting contents) (CM) (DH) (CH)

  • Page 110: Table 5.4 Information To Be Read By Identify Device Command

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3) Word Value Description...
  • Page 111 5.3 Host Commands Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3) Word Value Description 27-46 Set by a device Model name (ASCII code, 40 characters, left) X’8010’ Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command X’0000’...
  • Page 112 Interface Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3) Word Value Description Valid of command sets/function *14 Default of command sets/function *15 X’xx3F’ Ultra DMA transfer mode *16 Set by a device Security Erase Unit execution time (1 LSB: 2 min.) *21 X’0000’...
  • Page 113 5.3 Host Commands *19 Status of the Word 2 Identify information is shown as follows: 37C8h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete. 738Ch The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up.
  • Page 114 Interface Bit 2: 1 = Enable the word 88 Bit 1: 1 = Enable the word 64-70 Bit 0: 1 = Enable the word 54-58 *6 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command Bit 15-9: Reserved Bit 8: 1 = Enable the multiple sector transfer Bit 7-0:...
  • Page 115 5.3 Host Commands Bit 1-0: Undefined *10 WORD 82 Bit 15: Undefined Bit 14: '1' = Supports the NOP command. Bit 13: '1' = Supports the READ BUFFER command. Bit 12: '1' = Supports the WRITE BUFFER command. Bit 11: Undefined Bit 10: '1' = Supports the Host Protected Area feature set.
  • Page 116 Interface Bit 4: '1' = Supports the Removable Media Status Notification feature set. Bit 3: '1' = Supports the Advanced Power Management feature set. Bit 2: '1' = Supports the CFA (Compact Flash Association) feature set. Bit 1: '1' = Supports the READ/WRITE DMA QUEUED command. Bit 0: '1' = Supports the DOWNLOAD MICROCODE command.
  • Page 117 5.3 Host Commands Bit 0: '1' = From the SMART ENABLE OPERATION command *14 WORD 86 Bits 15: Reserved Bit 13-10: Same definition as WORD 83. Bit 9: '1' = Enables the Automatic Acoustic Management function. From the SET FEATURES command Bit 8: '1' = From the SET MAX SET PASSWORD command Bits 7-6:...
  • Page 118 Interface Bit 0: '1' = Supports the Mode 0 *21 WORD 89 MHS2060AT = X'14': 40 minutes MHS2030AT = X'0A': 20 minutes *17 WORD 93 Bits 15: Bit 14: = '1' Bit 13: '1' = CBLID- is a higher level than VIH (80-conductor cable). It is fixed at 1 in the MHS-series devices.
  • Page 119 5.3 Host Commands Bit 0: '1'= (In the case of device 0) *18 WORD 128 Bit 15-9: Reserved Bit 8: Security level. 0: High, 1: Maximum Bit 7-6: Reserved Bit 5: '1' = Enhanced security erase supported Bit 4: '1' = Security counter expired Bit 3: '1' = Security frozen Bit 2:...

  • Page 120: Table 5.5 Features Register Values And Settable Modes

    Interface Table 5.5 Features register values and settable modes Features Drive operation mode Register X’02’ Enables the write cache function. X’03’ Set the data transfer mode. *1 X’05’ Enables the advanced power management function. *2 X’42’ Enables the Acoustic management function. *3 X’55’...
  • Page 121 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) xx or *1~3 (FR) [See Table 5.5] At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information *1) Data Transfer Mode...
  • Page 122 Interface Multiword DMA transfer mode X 00100 000 (X’20’: Mode 0) 00100 001 (X’21’: Mode 1) 00100 010 (X’22’: Mode 2) Ultra DMA transfer mode X 01000 000 (X’40’: Mode 0) 01000 001 (X’41’: Mode 1) 01000 010 (X’42’: Mode 2) 01000 011 (X’43’: Mode 3) 01000 100 (X’44’: Mode 4) 01000 101 (X’45’: Mode 5)
  • Page 123 5.3 Host Commands (15) SET MULTIPLE MODE (X’C6’) This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands. The block count (number of sectors in a block) for these commands are also specified by the SET MULTIPLE MODE command.
  • Page 124 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) Sector count/block (FR) After power-on the READ MULTIPLE and WRITE MULTIPLE command operation are disabled as the default mode. At command completion (I/O registers contents to be read) (ST) Status information (DH)
  • Page 125 5.3 Host Commands SET MAX ADDRESS A successful READ NATIVE MAX ADDRESS command shall immediately precede a SET MAX ADDRESS command. This command allows the maximum address accessible by the user to be set in LBA or CHS mode. Upon receipt of the command, the device sets the BSY bit and saves the maximum address specified in the DH, CH, CL and SN registers.
  • Page 126 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information SET MAX SET PASSWORD (FR = 01h) This command requests a transfer of 1 sector of data from the host, and defines the contents of SET MAX password.
  • Page 127 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information Password information Words Contents Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved SET MAX LOCK (FR = 02h) The SET MAX LOCK command sets the device into SET_MAX_LOCK state.
  • Page 128 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX UNLOCK (FR = 03h) This command requests a transfer of single sector of data from the host, and defines the contents of SET MAX ADDRESS password.
  • Page 129 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information SET MAX FREEZE LOCK (FR=04h) The Set MAX FREEZE LOCK command sets the device to SET_MAX_Frozen state.
  • Page 130 Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) (CL) (SN) (SC) (FR) At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (17) READ NATIVE MAX ADDRESS (F8) This command posts the maximum address intrinsic to the device, which can be set by the SET MAX ADDRESS command.
  • Page 131 5.3 Host Commands At command completion (I/O registers contents to be read) (ST) Status information (DH) Max head/LBA [MSB] (CH) Max. cylinder [MSB]/Max. LBA (CL) Max. cylinder [LSB]/Max. LBA (SN) Max. sector/Max. LBA [LSB] (SC) (ER) Error information (18) EXECUTE DEVICE DIAGNOSTIC (X’90’) This command performs an internal diagnostic test (self-diagnosis) of the device.

  • Page 132: Table 5.6 Diagnostic Code

    Interface Table 5.6 Diagnostic code Code Result of diagnostic X’01’ No error detected. X’02’ HDC diagnostic error X’03’ Buffer diagnostic error X’04’ SRAM diagnostic error X’05’ MPU diagnostic error X’07’ ROM sum check error X’08’ Failure of HDC PVT cell X’09’...
  • Page 133 5.3 Host Commands (19) READ LONG (X’22’ or X’23’) This command operates similarly to the READ SECTOR(S) command except that the device transfers the data in the requested sector and the ECC bytes to the host system. The ECC error correction is not performed for this command. This command is used for checking ECC function by combining with the WRITE LONG command.
  • Page 134 Interface (20) WRITE LONG (X’32’ or X’33’) This command operates similarly to the READ SECTOR(S) command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium. The device does not generate ECC bytes by itself. The WRITE LONG command supports only single sector operation.
  • Page 135 5.3 Host Commands (21) READ BUFFER (X’E4’) The host system can read the current contents of the data buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt.
  • Page 136 Interface (22) WRITE BUFFER (X’E8’) The host system can overwrite the contents of the data buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data.
  • Page 137 5.3 Host Commands (23) IDLE (X’97’ or X’E3’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode.
  • Page 138 Interface At command completion (I/O registers contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (24) IDLE IMMEDIATE (X’95’ or X’E1’) Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode.
  • Page 139 5.3 Host Commands (25) STANDBY (X’96’ or X’E2’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the standby mode.
  • Page 140 Interface (26) STANDBY IMMEDIATE (X’94’ or X’E0’) Upon receipt of this command, the device sets the BSY bit of the Status register and enters the standby mode. The device then clears the BSY bit and generates an interrupt. This command does not support the automatic power-down sequence. At command issuance (I/O registers setting contents) (CM) X’94’...
  • Page 141 5.3 Host Commands (27) SLEEP (X’99’ or X’E6’) This command is the only way to make the device enter the sleep mode. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt.
  • Page 142 Interface (28) CHECK POWER MODE (X’98’ or X’E5’) The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by the contents of the Sector Count register. The device sets the BSY bit and sets the following register value.
  • Page 143 5.3 Host Commands (29) SMART (X’B0) This command predicts the occurrence of device failures depending on the subcommand specified in the FR register. If the FR register contains values that are not supported with the command, the Aborted Command error is issued. Before issuing the command, the host must set the key values in the CL and CH registers (4Fh in the CL register and C2h in the CH register).

  • Page 144: Table 5.7 Features Register Values (Subcommands) And Functions

    Interface Table 5.7 Features Register values (subcommands) and functions (1 of 3) Features Resister Function X’D0’ SMART Read Attribute Values: A device that received this subcommand asserts the BSY bit and saves all the updated attribute values. The device then clears the BSY bit and transfers 512-byte attribute value information to the host.
  • Page 145 5.3 Host Commands Table 5.7 Features Register values (subcommands) and functions (2 of 3) Features Resister Function X’D5’ SMART Read Log Sector: A device which receives this sub-command asserts the BSY bit, then reads the log sector specified in the SN register. Next, it clears the BSY bit and transmits the log sector to the host computer.
  • Page 146 Interface Table 5.7 Features Register values (subcommands) and functions (3 of 3) Features Resister Function X’DA’ SMART Return Status: When the device receives this subcommand, it asserts the BSY bit and saves the current device attribute values. Then the device compares the device attribute values with insurance failure threshold values.
  • Page 147 5.3 Host Commands At command completion (I-O registers setting contents) (ST) Status information (DH) (CH) Key-failure prediction status (C2h/2Ch) (CL) Key-failure prediction status (4Fh/F4h) (SN) (SC) (ER) Error information The attribute value information is 512-byte data; the format of this data is shown the following table 5.8.

  • Page 148: Table 5.8 Format Of Device Attribute Value Data

    Interface Table 5.8 Format of device attribute value data Byte Item Data format version number Attribute 1 Attribute ID Status flag Current attribute value Attribute value for worst case so far 07 to 0C Raw attribute value Reserved 0E to 169 Attribute 2 to (The format of each attribute value is the same as attribute 30...
  • Page 149 5.3 Host Commands Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds. The data format version numbers of the device attribute values and insurance failure thresholds are the same.
  • Page 150 Interface Status Flag Meaning If this bit is 1, it indicates normal operations are assured with the attribute when the attribute value exceeds the threshold value. If this bit is 1 (0), it indicates the attribute only updated by an on- line test (off-line test).
  • Page 151 5.3 Host Commands Status Byte Meaning 00h or 80h Off-line data acquisition is not executed. 02h or 82h Off-line data acquisition has ended without an error. 04h or 84h Off-line data acquisition is interrupted by a command from the host. 05h or 85h Off-line data acquisition has ended before completion because of a command from the host.
  • Page 152 Interface Off-line data collection capability Indicates the method of off-line data collection carried out by the drive. If the off-line data collection capability is 0, it indicates that off-line data collection is not supported. Meaning If this bit is 1, it indicates that the SMART EXECUTE OFF- LINE IMMEDATE sub-command (FR register = D4h) is supported.

  • Page 153: Table 5.10 Log Directory Data Format

    5.3 Host Commands Insurance failure threshold The limit of a varying attribute value. The host compares the attribute values with the thresholds to identify a failure. Table 5.10 Log Directory Data Format Byte Item SMART Logging Version Number of sectors of Address "01h" Reserved Number of sectors of Address "02h"...

  • Page 154: Table 5.11 Data Format Of Smart Summary Error Log

    Interface Table 5.11 Data format of SMART Summary Error Log Byte Item Version of this function Pointer for the latest "Error Log Data Structure" 02 to 31 Error log data Reserved structure Command data Device Control register value structure Features register value Sector Count register value Sector Number register value Cylinder Low register value...

  • Page 155: Table 5.11.1 Data Format Of Smart Comprehensive Error Log

    5.3 Host Commands Command data structure Indicates the command received when an error occurs. Error data structure Indicates the status register when an error occurs. Total number of drive errors Indicates total number of errors registered in the error log. Checksum Two's complementary for the lowest-order 1 byte that is obtained by adding 1 byte after another for as many as 511 bytes beginning from the top of the...

  • Page 156: Table 5.12 Smart Self Test Log Data Format

    Interface SMART Self Test The host computer can issue the SMART Execute Off-line Immediate sub- command (FR Register = D4h) and cause the device to execute a self test. When the self test is completed, the device saves the SMART self test log to the disk medium.
  • Page 157 5.3 Host Commands (30) SECURITY DISABLE PASSWORD (F6h) This command invalidates the user password already set and releases the lock function. The host transfers the 512-byte data shown in Table 5.13 to the device. The device compares the user password or master password in the transferred data with the user password or master password already set, and releases the lock function if the passwords are the same.

  • Page 158: Table 5.13 Contents Of Security Password

    Interface Table 5.13 Contents of security password Word Contents Control word Bit 0: Identifier 0 = Compares the user passwords. 1 = Compares the master passwords. Bits 1 to 15: Reserved 1 to 16 Password (32 bytes) 17 to 255 Reserved At command issuance (I-O register contents)) (CM)
  • Page 159 5.3 Host Commands (31) SECURITY ERASE PREPARE (F3h) The SECURITY ERASE UNIT command feature is enabled by issuing the SECURITY ERASE PREPARE command and then the SECURITY ERASE UNIT command. The SECURITY ERASE PREPARE command prevents data from being erased unnecessarily by the SECURITY ERASE UNIT command. Issuing this command during FROZEN MODE returns the Aborted Command error.
  • Page 160 Interface Although this command invalidates the user password, the master password is retained. To recover the master password, issue the SECURITY SET PASSWORD command and reset the user password. If the SECURITY ERASE PREPARE command is not issued immediately before this command is issued, the Aborted Command error is returned.
  • Page 161 5.3 Host Commands SECURITY ERASE UNIT FROZEN MODE is canceled when the power is turned off, or when hardware is reseted. If this command is reissued in FROZEN MODE, the command is completed and FROZEN MODE remains unchanged. Issuing this command during LOCKED MODE returns the Aborted Command error.

  • Page 162: Table 5.14 Contents Of Security Set Password Data

    Interface (SN) (SC) (FR) At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (34) SECURITY SET PASSWORD (F1h) This command enables a user password or master password to be set. The host transfers the 512-byte data shown in Table 5.14 to the device. The device determines the operation of the lock function according to the specifications of the Identifier bit and Security level bit in the transferred data.

  • Page 163: Table 5.15 Relationship Between Combination Of Identifier And Security Level, And Operation Of The Lock Function

    5.3 Host Commands Table 5.15 Relationship between combination of Identifier and Security level, and operation of the lock function Identifier Level Description User High The specified password is saved as a new user password. The lock function is enabled after the device is turned off and then on.
  • Page 164 Interface (35) SECURITY UNLOCK This command cancels LOCKED MODE. The host transfers the 512-byte data shown in Table 5.13 to the device. Operation of the device varies as follows depending on whether the host specifies the master password. When the master password is selected When the security level is LOCKED MODE is high, the password is compared with the master password already set.
  • Page 165 5.3 Host Commands At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (36) FLUSH CACHE (E7) This command is used to order to write every write cache data stored by the device into the medium. BSY bit is held at "1" until every data has been written normally or an error has occurred.
  • Page 166 Interface At command completion (I-O register contents to be read) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information (37) DEVICE CONFIGURATION (X'B1') Individual Device Configuration Overlay feature set commands are identified by the value placed in the Features register. The following table shows these Features register values.
  • Page 167 5.3 Host Commands At command completion (I-O register contents) (ST) Status information (DH) (CH) (CL) (SN) (SC) (ER) Error information DEVICE CONFIGURATION RESTORE (FR=C0h) The DEVICE CONFIGURATION RESTORE command disables any setting previously made by a DEVICE CONFIGURATION SET command and returns the content of the IDENTIFY DEVICE command response to the original settings as indicated by the data returned from the execution of a DEVICE CONFIGURATION IDENTIFY command.
  • Page 168 Interface DEVICE CONFIGURATION IDENTIFY (FR=C2h) The DEVICE CONFIGURATION IDENTIFY command returns a 512 byte data structure is shown in Table 5.16. The content of this data structure indicates the selectable commands, modes, and feature sets that the device is capable of supporting. If a DEVICE CONFIGURATION SET command has been issued reducing the capabilities, the response to an IDENTIFY DEVICE command will reflect the reduced set of capabilities, while the DEVICE CONFIGURATION IDENTIFY command will reflect the entire set of...

  • Page 169: Table 5.16 Device Configuration Identify Data Structure

    5.3 Host Commands Table 5.16 DEVICE CONFIGURATION IDENTIFY data structure Word Value Content X'0001' Data structure revision X'0007' Multiword DMA modes supported Bit 15-3: Reserved Bit 2: 1 = Multiword DMA mode 2 and below are supported Bit 1: 1 = Multiword DMA mode 1 and below are supported Bit 0: 1 = Multiword DMA mode 0 is supported X'003F'...

  • Page 170: 1F7 (Cm)

    Interface (38) READ NATIVE MAX ADDRESS EXT (27H) Description This command is used to assign the highest address that the device can initially set with the SET MAX ADDRESS EXT command. The maximum address is displayed in the CH, CL, SN registers of the device control register with HOB bit = 0, 1.
  • Page 171 5.3 Host Commands (39) SET MAX ADDRESS EXT (37H) Description This command limits specifications so that the highest address that can be accessed by users can be specified only in LBA mode. The address information specified with this command is set in words 1, 54, 57, 58, 60, 61, and 100 to 103 of the IDENTIFY DEVICE command response.

  • Page 172: 1F6 (Dh)

    Interface At command issuance (I/O registers setting contents) (CM) (DH) (CH) P SET MAX LBA (47-40) (CH) C SET MAX LBA (23-16) (CL) P SET MAX LBA (39-32) (CL) C SET MAX LBA (15-8) (SN) P SET MAX LBA (31-24) (SN) C SET MAX LBA (7-0) (SC) P...
  • Page 173 5.3 Host Commands At command issuance (I/O registers setting contents) (CM) (DH) (CH) P (CH) C (CL) P (CL) C (SN) P (SN) C (SC) P (SC) C (FR) P (FR) C C: Current P: Previous At command completion (I/O registers contents to be read) (ST) Status information (DH)
  • Page 174 Interface (41) WRITE DMA EXT (35H) Description This command is the extended command of the WRITE DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
  • Page 175 5.3 Host Commands (42) READ DMA EXT (25H) Description This command is the extended command of the READ DMA command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.

  • Page 176: 1F5 (Ch)

    Interface (43) WRITE MULTIPLE EXT (39H) Description This command is the extended command of the WRITE MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
  • Page 177 5.3 Host Commands (44) READ MULTIPLE EXT (29H) Description This command is the extended command of the READ MULTIPLE command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
  • Page 178 Interface (45) WRITE SECTOR (S) EXT (34H) Description This command is the extended command of the WRITE SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.
  • Page 179 5.3 Host Commands (46) READ SECTOR (S) EXT (24H) Description This command is the extended command of the READ SECTOR (S) command. The LBA specification is increased from 28 bits to 48 bits, and the maximum number of sectors that can be transferred by a single command is changed from 100h to 10000h.

  • Page 180: Table 5.17 Command Code And Parameters

    Interface 5.3.3 Error posting Table 5.17 lists the defined errors that are valid for each command. Table 5.17 Command code and parameters (1 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) ICRC INDF ABRT TK0NF DRDY READ SECTOR(S) WRITE SECTOR(S) READ MULTIPLE WRITE MULTIPLE...
  • Page 181 5.3 Host Commands Table 5.17 Command code and parameters (2 of 2) Command name Error register (X’1F1’) Status register (X’1F7’) ICRC INDF ABRT TK0NF DRDY SLEEP CHECK POWER MODE SMART SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY SET PASSWORD SECURITY UNLOCK FLUSH CACHE...

  • Page 182: Command Protocol

    Interface 5.4 Command Protocol The host should confirm that the BSY bit of the Status register of the device is 0 prior to issue a command. If BSY bit is 1, the host should wait for issuing a command until BSY bit is cleared to 0. Commands can be executed only when the DRDY bit of the Status register is 1.
  • Page 183 5.4 Command Protocol words, the host should receive the relevant sector of data (512 bytes of uninsured dummy data) or release the DRQ status by resetting. Figure 5.3 shows an example of READ SECTOR(S) command protocol, and Figure 5.4 shows an example protocol for command abort. Figure 5.3 Read Sector(s) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register...

  • Page 184: Pio Data Transferring Commands From Host To Device

    Interface device to starting of the sector data transfer. Note that the host does not need to read the Status register for the reading of a single sector or the last sector in multiple-sector reading. If the timing to read the Status register does not meet above condition, normal data transfer operation is not guaranteed.
  • Page 185 5.4 Command Protocol The execution of these commands includes the transfer one or more sectors of data from the host to the device. In the WRITE LONG command, 516 bytes are transferred. Following shows the protocol outline. a) The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head registers.

  • Page 186: Commands Without Data Transfer

    Interface 40 ms Figure 5.5 WRITE SECTOR(S) command protocol IMPORTANT For transfer of a sector of data, the host needs to read Status register (X’1F7’) in order to clear INTRQ (interrupt) signal. The Status register should be read within a period from the DRQ setting by the device to starting of the sector data transfer.
  • Page 187 5.4 Command Protocol SEEK READY VERIFY SECTOR(S) EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE SET MAX ADDRESS (EXT) READ NATIVE MAX ADDRESS (EXT) IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE CHECK POWER MODE SMART DISABLE OPERATION SMART ENABLE/DISABLE AUTOSAVE SMART ENABLE OPERATION SMART EXECUTE OFFLINE IMMEDIATE SMART RETURN STATUS...

  • Page 188: Other Commands

    Interface 5.4.4 Other commands READ MULTIPLE (EXT) SLEEP WRITE MULTIPLE (EXT) See the description of each command. 5.4.5 DMA data transfer commands READ DMA (EXT) WRITE DMA (EXT) Starting the DMA transfer command is the same as the READ SECTOR(S) or WRITE SECTOR(S) command except the point that the host initializes the DMA channel preceding the command issuance.
  • Page 189 5.4 Command Protocol The interrupt processing for the DMA transfer differs the following point. The interrupt processing for the DMA transfer differs the following point. a) The host writes any parameters to the Features, Sector Count, Sector Number, Cylinder, and Device/Head register. b) The host initializes the DMA channel c) The host writes a command code in the Command register.
  • Page 190 Interface Figure 5.7 Normal DMA data transfer 5-114 C141-E171-03EN...

  • Page 191: Ultra Dma Feature Set

    5.5 Ultra DMA Feature Set 5.5 Ultra DMA Feature Set 5.5.1 Overview Ultra DMA is a data transfer protocol used with the READ DMA and WRITE DMA commands. When this protocol is enabled it shall be used instead of the Multiword DMA protocol when these commands are issued by the host.

  • Page 192: Phases Of Operation

    Interface device compares its CRC data to the data sent from the host. If the two values do not match the device reports an error in the error register at the end of the command. If an error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.
  • Page 193 5.5 Ultra DMA Feature Set 8) The device may assert DSTROBE t after the host has asserted DMACK-. ZIORDY Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated DMACK- at the end of an Ultra DMA burst.
  • Page 194 Interface NOTE - The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate HDMARDY- and wait t before asserting STOP.
  • Page 195 5.5 Ultra DMA Feature Set 6) The host shall drive DD (15:0) no sooner than t after the device has negated DMARQ. For this step, the host may first drive DD (15:0) with the result of its CRC calculation (see 5.5.5): 7) If DSTROBE is negated, the device shall assert DSTROBE within t after the host has asserted STOP.
  • Page 196 Interface after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and t timing for the device. 5) The host shall assert STOP no sooner than t after negating HDMARDY-.

  • Page 197: Ultra Dma Data Out Commands

    5.5 Ultra DMA Feature Set 5.5.4 Ultra DMA data out commands 5.5.4.1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.7 and 5.6.3.2 for specific timing requirements): 1) The host shall keep DMACK- in the negated state before an Ultra DMA burst is initiated.
  • Page 198 Interface 2) The host shall generate an HSTROBE edge to latch the new word no sooner than t after changing the state of DD (15:0). The host shall generate an HSTROBE edge no more frequently than t for the selected Ultra DMA Mode.
  • Page 199 5.5 Ultra DMA Feature Set 5.5.4.4 Terminating an Ultra DMA data out burst a) Host terminating an Ultra DMA data out burst The following stops shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.10 and 5.6.3.2 for specific timing requirements): 1) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
  • Page 200 Interface b) Device terminating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed (see 5.6.3.11 and 5.6.3.2 for specific timing requirements): 1) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.

  • Page 201: Ultra Dma Crc Rules

    5.5 Ultra DMA Feature Set 13) The host shall neither negate STOP nor HSTROBE until at least t after negating DMACK-. 14) The host shall not assert DIOW-, CS0-, CS1-, DA2, DA1, or DA0 until at least t after negating DMACK. 5.5.5 Ultra DMA CRC rules The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at...

  • Page 202: Series Termination Required For Ultra Dma

    Interface The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1. Note: Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic shall then be equivalent to shifting sixteen bits serially through the generator polynomial where DD0 is shifted in first and DD15 is shifted in last.

  • Page 203: Pio Data Transfer

    5.5 Ultra DMA Feature Set 5.6 Timing 5.6.1 PIO data transfer Figure 5.9 shows of the data transfer timing between the device and the host system. Addresses DIOR-/DIOW- Write data DD0-DD15 Read data DD0-DD15 IORDY Symbol Timing parameter Min. Max. Unit Cycle time —...
  • Page 204 Interface 5.6.2 Multiword data transfer Figure 5.10 shows the multiword DMA data transfer timing between the device and the host system. DMACK- DIOR-/DIOW- Symbol Timing parameter Min. Max. Unit Cycle time — Pulse width of DIOR-/DIOW- — Data Access time for DIOR- —...

  • Page 205: Ultra Dma Data Transfer

    5.5 Ultra DMA Feature Set 5.6.3 Ultra DMA data transfer Figures 5.11 through 5.20 define the timings associated with all phases of Ultra DMA bursts. Table 5.18 contains the values for the timings for each of the Ultra DMA Modes. 5.6.3.1 Initiating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

  • Page 206: Table 5.18 Ultra Dma Data Burst Timing Requirements

    Interface 5.6.3.2 Ultra DMA data burst timing requirements Table 5.18 Ultra DMA data burst timing requirements (1 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT...
  • Page 207 5.5 Ultra DMA Feature Set Table 5.18 Ultra DMA data burst timing requirements (2 of 2) NAME MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Limited interlock time (*1)

  • Page 208: Table 5.19 Ultra Dma Sender And Recipient Timing Requirements

    Interface Table 5.19 Ultra DMA sender and recipient timing requirements MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 (in ns) (in ns) (in ns) (in ns) (in ns) (in ns) NAME COMMENT MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX 14.7 Recipient IC data setup time (from DSIC...
  • Page 209 5.5 Ultra DMA Feature Set 5.6.3.3 Sustained Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC 2CYC DSTROBE at device DVHIC DVSIC DVHIC DVSIC DVHIC DD(15:0) at device DSTROBE at host DHIC DHIC...
  • Page 210 Interface 5.6.3.4 Host pausing an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) DSTROBE (device) DD(15:0) (device) Notes: 1) The host may assert STOP to request termination of the Ultra DMA burst no sooner than t after HDMARDY- is negated.
  • Page 211 5.5 Ultra DMA Feature Set 5.6.3.5 Device terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0-, CS1- Note:...
  • Page 212 Interface 5.6.3.6 Host terminating an Ultra DMA data in burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) HDMARDY- (host) IORDYZ DSTROBE (device) DD(15:0) DA0, DA1, DA2, CS0, CS1 Note: The definitions for the STOP, HDMARDY- and DSTROBE signal lines are no longer in effect after DMARQ and DMACK- are negated.
  • Page 213 5.5 Ultra DMA Feature Set 5.6.3.7 Initiating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) ZIORDY DDMARDY- (device) HSTROBE (host) DZFS DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1-...
  • Page 214 Interface 5.6.3.8 Sustained Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. 2CYC HSTROBE 2CYC at host DVHIC DVHIC DVHIC DVSIC DVSIC DD(15:0) at host HSTROBE at device DHIC DSIC DHIC DSIC DHIC...
  • Page 215 5.5 Ultra DMA Feature Set 5.6.3.9 Device pausing an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) DDMARDY- (device) HSTROBE (host) DD(15:0) (host) Notes: 1) The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than t...
  • Page 216 Interface 5.6.3.10 Host terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2 CS0-, CS1- Note: The definitions for the STOP, DDMARDY- and HSTROBE signal lines are...
  • Page 217 5.5 Ultra DMA Feature Set 5.6.3.11 Device terminating an Ultra DMA data out burst 5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes. DMARQ (device) DMACK- (host) STOP (host) IORDYZ DDMARDY- (device) HSTROBE (host) DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1-...

  • Page 218: Power-On And Reset

    Interface 5.6.4 Power-on and reset Figure 5.21 shows power-on and reset (hardware and software reset) timing. (1) Only master device is present Clear Reset *1 Power-on RESET- Software reset DASP- *1: Reset means including Power-on-Reset, Hardware Reset (RESET-), and Software Reset. (2) Master and slave devices are present (2-drives configuration) Clear Reset [Master device]...

  • Page 219: Chapter 6 Operations

    CHAPTER 6 Operations Device Response to the Reset Power Save Defect Processing Read-Ahead Cache Write Cache C141-E171-03EN...

  • Page 220: Device Response To The Reset

    Operations 6.1 Device Response to the Reset This section describes how the PDIAG- and DASP- signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command. 6.1.1 Response to power-on After the master device (device 0) releases its own power-on reset state, the master device shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).

  • Page 221: Response To Hardware Reset

    6.1 Device Response to the Reset Power on Master device Power On Reset- Status Reg. BSY bit Max. 31 sec. Checks DASP- for up to If presence of a slave device is 450 ms. confirmed, PDIAG- is checked for up to 31 seconds. Slave device Power On Reset- BSY bit...
  • Page 222 Operations After the slave device receives the hardware reset, the slave device shall report its presence and the result of the self-diagnostics to the master device as described below: DASP- signal: Asserted within 400 ms. PDIAG- signal: Negated within 1 ms and asserted within 30 seconds. The asserted PDIAG-signal is negated 30 seconds after it is asserted if the command is not received.

  • Page 223: Response To Software Reset

    6.1 Device Response to the Reset 6.1.3 Response to software reset The master device does not check the DASP- signal for a software reset. If a slave device is present, the master device checks the PDIAG- signal for up to 15 seconds to see if the slave device has completed the self-diagnosis successfully.

  • Page 224: Response To Diagnostic Command

    Operations 6.1.4 Response to diagnostic command When the master device receives an EXECUTE DEVICE DIAGNOSTIC command and the slave device is present, the master device checks the PDIAG- signal for up to 6 seconds to see if the slave device has completed the self- diagnosis successfully.

  • Page 225: Power Save

    6.2 Power Save 6.2 Power Save The host can change the power consumption state of the device by issuing a power command to the device. 6.2.1 Power save mode There are five types of power consumption state of the device including active mode where all circuits are active.
  • Page 226 Operations Upon receipt of a hard reset Upon receipt of Idle/Idle Intermediate (4) Standby mode In this mode, the spindle motor has stopped from the low power idle state. The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active, active idle, or low power idle mode because the access to the disk medium cannot be made immediately.

  • Page 227: Defect Processing

    6.3 Defect Processing 6.2.2 Power commands The following commands are available as power commands. IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES (APM setting) 6.3 Defect Processing This device performs alternating processing where the defective sector is alternated with the spare area depending on media defect location information.

  • Page 228: Alternating Processing For Defective Sectors

    Operations 6.3.2 Alternating processing for defective sectors The following two types of technology are used for alternating processing: (1) Sector slip processing In this method, defective sectors are not used (thereby avoiding the effects of defects), and each defective sector is assigned to the next contiguous sector that is normal.
  • Page 229 6.3 Defect Processing Sector (physical) Defec- Cylinder 0 tive Head 0 sector (Not used) Alternate cylinder 0 Head 0 This is assigned to an unassigned sector. Already assigned Notes: 1. The alternate cylinder is assigned to an inner cylinder in each zone. 2.

  • Page 230: Read-Ahead Cache

    Operations 6.4 Read-ahead Cache Read-ahead Cache is the function for automatically reading data blocks upon completion of the read command in order to read data from disk media and save data block on a data buffer. If a subsequent command requests reading of the read-ahead data, data on the data buffer can be transferred without accessing the disk media.
  • Page 231 6.4 Read-ahead Cache (1) Commands that are targets of caching The commands that are targets of caching are as follows: READ SECTOR(S (EXT) READ MULTIPLE (EXT) READ DMA (EXT) However, if the caching function is prohibited by the SET FEATURES command, the caching operation is not performed.
  • Page 232 Operations 1)-2 Commands that partially invalidate caching data (When data in the buffer or on media is overwritten, the overwritten data is invalidated.) READ DMA / READ MULTIPLE / READ SECTOR (S) READ DMA EXT / READ MULTIPLE EXT / READ SECTOR (S) EXT WRITE DMA / WRITE MULTIPLE / WRITE SECTOR (S) WRITE DMA EXT / WRITE MULTIPLE EXT / WRITE SECTOR (S) EXT SET MAX ADDRESS...

  • Page 233: Using The Read Segment Buffer

    6.4 Read-ahead Cache 6.4.3 Using the read segment buffer Methods of using the read segment buffer are explained for the following situations. 6.4.3.1 Miss-hit (no hit) In this situations, the top block of read requested data is not stored at all in the data buffer.
  • Page 234 Operations 4) The following cache valid data is for the read command that is executed next: Cache valid data START LBA (Logical block address) LAST LBA 6.4.3.2 Sequential reading The read-ahead operation is performed for the read buffer when the read command that is targeted at a sequential address is received after execution of the read command is completed.
  • Page 235 6.4 Read-ahead Cache b. Sequential hit When the end sector address of the read command received the last time and the top sector address of the read command this time are consecutive, hit data already stored on the buffer is transferred to the host system. At the same time as a transfer of the hit data to the host system starts, the new read-ahead operation for the subsequent data is implemented in the free space that has been made available by the data transfer.
  • Page 236 Operations 6.4.3.3 Full hit In this situation, all read requested data is stored in the data buffer. Transfer of the read requested data is started from the location where hit data is stored. For data that is a target of caching and remains before a full hit, the data is retained when execution of the command is completed.
  • Page 237 6.4 Read-ahead Cache 6.4.3.4 Partial hit In this situation, a part of read requested data including the top sector is stored in the data buffer. A transfer of the read requested data starts from the address where the data that is hit is stored until the top sector of the read requested data. Remaining part of insufficient data is read then.

  • Page 238: Write Cache

    Operations 6.5 Write Cache Write Cache is the function for reducing the command processing time by separating command control to disk media from write control to disk media. When Write Cache is permitted, the write command can be keep receiving as long as the space available for data transfers remains free on the data buffer.
  • Page 239 6.5 Write Cache (3) Status report in the event of an error The status report concerning an error occurring during writing onto media is created when the next command is issued. Where the command reporting the error status is not executed, only the error status is reported. Only the status of an error that occurs during write processing is reported.
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  • Page 241 Glossary Actuator Head positioning assembly. The actuator consists of a voice coil motor and head arm. If positions the read-write (R-W) head. AT bus A bus between the host CPU and adapter board ATA (AT Attachment) standard The ATA standard is for a PC AT interface regulated to establish compatibility between products manufactured by different vendors.
  • Page 242 Glossary MTBF Mean time between failures. The MTBF is calculated by dividing the total operation time (total power-on time) by the number of failures in the disk drive during operation. MTTR Mean time to repair. The MTTR is the average time required for a service person to diagnose and repair a faulty drive.
  • Page 243 Glossary Status The status is a piece of one-byte information posted from the drive to the host when command execution is ended. The status indicates the command termination state. Voice coil motor. The voice coil motor is excited by one or more magnets. In this drive, the VCM is used to position the heads accurately and quickly.
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  • Page 245: Acronyms And Abbreviations

    Acronyms and Abbreviations Hard disk drive ABRT Aborted command Automatic idle control IDNF ID not found AMNF Address mark not found IRQ14 Interrupt request 14 AT attachment American wire gage Light emitting diode Bad block detected BIOS Basic input-output system Mega-byte MB/S Mega-byte per seconds...
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  • Page 247 Index active idle mode 6-7 fluctuation,current 1-7 active mode 6-7 full hit 6-18 alternate cylinder assignment processing 6-10 alternating processing, hit, full 6-18 automatic 6-11 hit, no 6-15 for defective sector 6-10 hit, partial 6-19 for defective sector 6-10 hit, sequential 6-17 area, spare 6-9 host pausing Ultra DMA data in burst assignment processing, alternate cylinder...
  • Page 248 Index status report in event of error 6-20 sustain, Ultra DMA data operation 6-1 in burst 5-133 operation, caching 6-12 out burst 5-138 operation, read-ahead 6-12 sustained Ultra DMA data in burst 5-133 out burst 5-138 partial hit 6-19 pausing, device Ultra DMA data out burst 5-139 terminating, device Ultra DMA data out pausing, host Ultra DMA data in burst...
  • Page 249 List any errors or suggestions for improvement. Page Line Contents Please send this form to the address below. We will use your comments in planning future editions. Address: Fujitsu Learning Media Limited 37-10 Nishikamata 7-chome Oota-ku Tokyo 144-0051 JAPAN Fax: 81-3-3730-3702...
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  • Page 251 MHS2060AT, MHS2040AT MHS2030AT, MHS2020AT DISK DRIVES C141-E171-03EN PRODUCT MANUAL MHS2060AT, MHS2040AT MHS2030AT, MHS2020AT DISK DRIVES C141-E171-03EN PRODUCT MANUAL...
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