Intel 520J - Pentium 4 2.80GHz 800MHz 1MB Socket 775 CPU Datasheet page 73

Table 4-3. Signal Description (Sheet 8 of 8)
Name
VID[5:0]
VSS
VSSA
VSS_SENSE
VSS_MB_
REGULATION
VTT
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_SEL
VTTPWRGD
Datasheet
Type
VID[5:0] (Voltage ID) signals are used to support automatic selection of power
supply voltages (V
CC
processor and must be pulled up on the motherboard. Refer to the Voltage
Regulator-Down (VRD) 10.1 Design Guide for Desktop Socket 775 for more
information. The voltage supply for these signals must be valid before the VR
Output
can supply V to the processor. Conversely, the VR output must be disabled
CC
until the voltage supply for the VID signals becomes valid. The VID signals are
needed to support the processor voltage specification variations. See
for definitions of these signals. The VR must supply the voltage that is
requested by the signals, or disable itself.
VSS are the ground pins for the processor and should be connected to the
Input
system ground plane.
Input VSSA is the isolated ground for internal PLLs.
VSS_SENSE is an isolated low impedance connection to processor core V
Output
can be used to sense or measure ground near the silicon with little noise.
This land is provided as a voltage regulator feedback sense point for V
connected internally in the processor package to the sense point land V27 as
Output
described in the Voltage Regulator-Down (VRD) 10.1 Design Guide for Desktop
Socket 775.
Miscellaneous voltage supply.
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a
voltage supply for some signals that require termination to V
motherboard.
For future processor compatibility some signals are required to be pulled up to
VTT_OUT_LEFT or VTT_OUT_RIGHT. Refer to the following table for the
signals that should be pulled up to VTT_OUT_LEFT and VTT_OUT_RIGHT.
Output
Pull-up Signal
VTT_OUT_RIGHT
VTT_OUT_LEFT
The VTT_SEL signal is used to select the correct V
Output
processor.
The processor requires this input to determine that the V
Input
and within specification.
§
Land Listing and Signal Descriptions
Description
). These are open drain signals that are driven by the
Signals to be Pulled Up
VTT_PWRGOOD, VID[5:0], GTLREF, TMS, TDI,
TDO, BPM[5:0], other VRD components
RESET#, BR0#, PWRGOOD, TESTHI1, TESTHI8,
TESTHI9, TESTHI10, TESTHI11, TESTHI12
Table 2-2
. It
SS
. It is
SS
on the
TT
voltage level for the
TT
voltages are stable
TT
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