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AMD Athlon™ XP Processor Model 8 Data Sheet
Table 16. General AC and DC Characteristics (continued)
Symbol
Parameter Description
T
Input Time to Acquire
BIT
T
Input Time to Reacquire
RPT
T
Signal Rise Time
RISE
T
Signal Fall Time
FALL
C
Pin Capacitance
P
IN
T
Time to data valid
VALID
Notes:
1. Characterized across DC supply voltage range.
2. Values specified at nominal V
3. I
and I
are measured at V
OL
OH
4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.
5. These are aggregate numbers.
6. Edge rates indicate the range over which inputs were characterized.
7. In asynchronous operation, the signal must persist for this time to enable capture.
8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.
9. The approximate value for standard case in normal mode operation.
10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.
11. Reassertions of the signal within this time are not guaranteed to be seen by the core.
12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.
13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other
configurations.
14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the "Power-Up Timing Requirements" chapter for more
information.
40
Preliminary Information
Condition
. Scale parameters between V
CC_CORE
maximum and V
minimum, respectively.
OL
OH
Electrical Data
Min
20.0
40.0
1.0
1.0
4
minimum and V
CC_CORE.
CC_CORE.
25175H—March 2003
Max
Units Notes
ns
7, 8
ns
9–13
3.0
V/ns
6
3.0
V/ns
6
12
pF
100
ns
14
maximum.
Chapter 8
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