Xilinx LogiCORE IP CAN 3.2 Getting Started Manual page 26

Chapter 4: Detailed Example Design
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Core with Acceptance Filtering
The demonstration test bench performs the following tasks:
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Five messages are written in sequence:
The first message is written to the TXHPB and is a standard data frame.
The second message is written to the TX FIFO and is a standard data frame.
The third message is written to the TX FIFO and is a standard remote frame.
The fourth message is written to the TX FIFO and is an extended data frame.
The fifth message is written to the TX FIFO and is an extended remote frame.
After each message is written, the test bench waits for the assertion of the interrupt
line. When the interrupt line is asserted, the following conditions occur:
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The bits set in the ISR are displayed.
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The RX FIFO is read if the RXOK bit is set. The message received is compared
with the message previously transmitted.
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The ICR is written to. This clears the bits in the ISR that are set.
With no acceptance filtering, all five messages are received in the RX FIFO.
Input clock signals are generated.
A reset is applied to the example design.
The Baud Rate Prescalar register and Bit Timing registers are written to. These
registers are read from and the values read are compared with the values written.
The Interrupt Enable Register is written to enable interrupts for TXBFLL and RXOK
bits. This register is read from and the value read is compared with the value written.
Acceptance Filter ID Register 1 and Acceptance Filter Mask Register 1 are written to.
These registers are read from and the values read are compared with the values
written.
The Acceptance Filter Register is written to enable Acceptance Filter pair 1. This
register is read from and the value read is compared with the value written.
The Mode Select Register is written to select Loop Back mode. This register is read
from and the value read is compared with the value written.
The Software Reset Register is written to enable CEN bit. This register is read from
and the value written is compared with the value read.
Five messages are written in a sequence.
The first message is written to the TXHPB and is a standard data frame.
The second message is written to the TX FIFO and is a standard data frame.
The third message is written to the TX FIFO and is a standard remote frame.
The fourth message is written to the TX FIFO and is an extended data frame.
The fifth message is written to the TX FIFO and is an extended remote frame.
After each message is written, the test bench waits for the interrupt line to be asserted.
When the interrupt line is asserted, the following conditions occur:
♦
The bits in the ISR that are set are displayed.
♦
The RX FIFO is read if the RXOK bit is set. The message that is received is
compared with the message that was transmitted.
♦
The ICR is written to. This clears the bits in the ISR that are set.
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UG186 April 19, 2010