Simulation/Timing - Xilinx LogiCORE IP CAN 3.2 Getting Started Manual

Chapter 4: Detailed Example Design

simulation/timing

The timing simulation directory is generated only for Full-System Hardware Evaluation
and Full-license types.
Table 4-9: Timing Directory
22
Name
<project_dir>/<component_name>/simulation/timing
simulate_mti.do
simulate_ncsim.sh
simulate_ncsim.bat
wave.do
wave.sv
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Description
A macro file for ModelSim that compiles the
post-par timing netlist, demonstration test
bench files, and runs the simulation.
A macro file for Cadence IES that compiles
the post-par timing netlist, demonstration
test bench files, and runs the simulation in a
Linux environment.
A macro file for Cadence IES that compiles
the post-par timing netlist, demonstration
test bench files, and runs the simulation in a
Windows environment.
A macro file for ModelSim that opens a wave
window and adds key signals to the wave
viewer. This file is called by the
simulate_mti.do file and is displayed after
the simulation is loaded.
A macro file for Cadence IES that opens a
wave window and adds key signals to the
wave viewer.
CAN Getting Started Guide
UG186 April 19, 2010