Embedded Bios Post Codes - Intel 440BX Manual

BIOS Quick Reference
A complete discussion of the debugger is beyond the scope of this chapter; however, complete
documentation is available from General Software via the web at http://www.gensw.com.
5.11

Embedded BIOS POST Codes

Embedded BIOS writes progress codes, also known as POST codes, to I/O port 80H during POST,
in order to provide information to OEM developers about system faults. These POST codes may be
monitored on the on-board Post Code Debugger located at U12 and U13. They are not displayed on
the screen. For more information about POST codes, contact General Software.
Mnemonic Code
POST_STATUS_START
POST_STATUS_CPUTEST
POST_STATUS_DELAY
POST_STATUS_DELAYDONE
POST_STATUS_KBDBATRDY
POST_STATUS_DISABSHADOW
POST_STATUS_CALCCKSUM
POST_STATUS_CKSUMGOOD
POST_STATUS_BATVRFY
POST_STATUS_KBDCMD
POST_STATUS_KBDDATA
POST_STATUS_BLKUNBLK
POST_STATUS_KBDNOP
POST_STATUS_SHUTTEST
POST_STATUS_CMOSDIAG
POST_STATUS_CMOSINIT
POST_STATUS_CMOSSTATUS
POST_STATUS_DISABDMAINT
POST_STATUS_DISABPORTB
POST_STATUS_BOARD
POST_STATUS_TESTTIMER
POST_STATUS_TESTTIMER2
POST_STATUS_TESTTIMER1
POST_STATUS_TESTTIMER0
POST_STATUS_MEMREFRESH
POST_STATUS_TESTREFRESH
POST_STATUS_TEST15US
POST_STATUS_TEST64KB
POST_STATUS_TESTDATA
POST_STATUS_TESTADDR
POST_STATUS_TESTPARITY
POST_STATUS_TESTMEMRDWR
POST_STATUS_SYSINIT
POST_STATUS_INITVECTORS
POST_STATUS_8042TURBO
POST_STATUS_POSTTURBO
POST_STATUS_POSTVECTORS
POST_STATUS_MONOMODE
POST_STATUS_COLORMODE
POST_STATUS_TOGGLEPARITY
POST_STATUS_INITBEFOREVIDEO
POST_STATUS_VIDEOROM
52
Code System Progress Report
00h Start POST (BIOS is executing).
01h Start CPU register test.
02h Start power-on delay.
03h Power-on delay finished.
04h Keyboard BAT finished.
05h Disable shadowing & cache.
06h Compute ROM CRC, wait for KBC.
07h CRC okay, KBC ready.
08h Verifying BAT command to KB.
09h Start KBC command.
0ah Start KBC data.
0bh Start pin 23,24 blocking & unblocking.
0ch Start KBC NOP command.
0dh Test CMOS RAM shutdown register.
0eh Check CMOS checksum.
0fh Initialize CMOS contents.
10h Initialize CMOS status for date/time.
11h Disable DMA, PICs.
12h Disable Port B, video display.
13h Initialize board, start memory bank detection.
14h Start timer tests.
15h Test 8254 T2, for speaker, port B.
16h Test 8254 T1, for refresh.
17h Test 8254 T0, for 18.2Hz.
18h Start memory refresh.
19h Test memory refresh.
1ah Test 15usec refresh ON/OFF time.
1bh Test base 64KB memory.
1ch Test data lines.
20h Test address lines.
21h Test parity (toggling).
22h Test Base 64KB memory.
23h Prepare system for IVT initialization.
24h Initialize vector table.
25h Read 8042 for turbo switch setting.
26h Initialize turbo data.
27h Modification of IVT.
28h Video in monochrome mode verified.
29h Video in color mode verified.
2ah Toggle parity before video ROM test.
2bh Initialize before video ROM check.
2ch Passing control to video ROM.
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Intel 440Bx Scalable Performance Board Development Kit Manual