Configuration Registers; Chapter 8: Configuration And Status - Xilinx LogiCORE IP MAC v8.5 User Manual

Ug144 1-gigabit ethernet
Table of Contents

Advertisement

R

Configuration Registers

After a power-up or system reset, the client may reconfigure the core parameters using
their defaults. Configuration changes can be written at any time. Both the receiver and
transmitter logic responds only to configuration changes during inter-frame gaps. The
exceptions to this are the configurable resets that take effect immediately.
Configuration of the GEMAC core is performed through a register bank that is accessed
through the management interface. The configuration registers available in the core are
listed in
address in the ranges shown performs a 32-bit read or write from the same configuration
word.
Table 8-2: Configuration Registers
78
-- DISCONTINUED PRODUCT --
Table
8-2. As shown, the address has some implicit don't care bits; any access to an
Address
0x200-0x23F
Receiver Configuration (Word 0)
0x240-0x27F
Receiver Configuration (Word 1)
0x280-0x2BF
Transmitter Configuration
0x2C0-0x2FF
Flow Control Configuration
0x300-0x33F
Reserved
0x340-0x37F
Management Configuration
0x380-0x383
Unicast Address (Word 0) (if Address Filter is present)
0x384-0x387
Unicast Address (Word 1) (if Address Filter is present)
0x388-0x38B
Address Table Configuration (Word 0) (if Address Filter is
present)
0x38C-0x38F
Address Table Configuration (Word 1) (if Address Filter is
present)
0x390-0x393
Address Filter Mode (if Address Filter is present)
www.xilinx.com

Chapter 8: Configuration and Status

Description
1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009

Advertisement

Table of Contents
loading

Table of Contents