Ld %R,Imm - Epson S1C63000 Core Cpu Manual

Seiko epson s1c63000 cmos 4-bit single chip microcomputer core cpu manual
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CHAPTER 4: INSTRUCTION SET

LD %r,imm4

Function: r
imm4
Loads the 4-bit immediate data imm4 into the r register (A, B or F).
Code:
Mnemonic
LD %A,imm4
LD %B,imm4
LD %F,imm4
Flags:
E
I
Src: Immediate data
Mode:
Dst: Register direct
Extended addressing: Invalid
LD %r,[%ir]
Function: r
[ir]
Loads the content of the data memory addressed by the ir register (X or Y) into the r register (A
or B).
Code:
Mnemonic
LD %A,[%X]
LD %A,[%Y]
LD %B,[%X]
LD %B,[%Y]
E
I
Flags:
Src: Register indirect
Mode:
Dst: Register direct
Extended addressing: Valid
Extended LDB
%EXT,imm8
operation: LD
%r,[%X]
LDB
%EXT,imm8
LD
%r,[%Y]
100
Load immediate data imm4 into r reg.
MSB
1 1 1 1 0 1 1 0 0 i3 i2 i1 i0 1EC0H–1ECFH
1 1 1 1 0 1 1 0 1 i3 i2 i1 i0 1ED0H–1EDFH
1 0 0 0 0 1 0 1 1 i3 i2 i1 i0 10B0H–10BFH
C
Z
(r = F)
Load location [ir reg.] into r reg.
MSB
1 1 1 1 0 1 1 1 0 0 0 0 0
1 1 1 1 0 1 1 1 0 0 0 1 0
1 1 1 1 0 1 1 1 0 0 1 0 0
1 1 1 1 0 1 1 1 0 0 1 1 0
C
Z
r
[00imm8] (00imm8 = 0000H + 00H to FFH)
r
[FFimm8] (FFimm8 = FF00H + 00H to FFH)
EPSON
LSB
LSB
1EE0H
1EE2H
1EE4H
1EE6H
S1C63000 CORE CPU MANUAL
1 cycle
1 cycle

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