Hpmc Caused By A Multi-Bit Memory Parity Error; Pim Action Table - HP Model 712/100 - Workstation Handbook

Table 4–1. PIM Action Table
Check Type Cache Check Bus Check
Word Word
0x80000000 0x40000000
0x20000000 N/A
0x20000000 N/A
0x20000000 N/A
0x20000000 N/A
Note 1 When more than one failed FRU is identified, run the appropriate diagnos-
tics to isolate the failed FRU.
Note 2 While Architected Main Memory space is from 0x00000000 through
0xEFFFFFFF, the Model 712 can only use up to 128 MB (192 MB for the
712/100). With this limitation any memory address from 0x10000000
(0X14000000 for the 712/100) through 0xEFFFFFFF is invalid, and, if giv-
en in the System Responder word, the Motherboard should (usually) be re-
placed. If the error occurs again, there is a probable Kernel problem.
See HPMC Caused by a Multi-Bit Memory Parity Error for information on
identifying the failed SIMM.

HPMC Caused by a Multi-Bit Memory Parity Error

An HPMC interruption is forced when a multi-bit memory parity error is detected
during a "DMA read" operation of fetching an I/D cache line (32 bytes).
Examine the 12 words listed under Other Processor Data of the data returned from a
pim command during the Boot Administration environment. These words represent
the following data:
Other Processor Data
IIA Space IIA Offset
Reserved Cache Check
Assists Check Reserved
Table 4–2 shows an example of the values for these words:
System
Word Responder
Word
N/A N/A
0X00210000 0X00000000
0xEFFFFFFF
0x00310000 0xF0000000
0xF01FFFFF
0x00310000 0xF0200000
0xFFBFFFFF
0x00310000 0xFFFBF000
0xFFFFFFFF
Check Type CPU State
TLB Check Bus Check
Assist State System Responder Address
Troubleshooting
Action *
See Note 1
Replace
Motherboard
Replace SIMM
See Note 2
Replace
Motherboard
Replace Optional
I/O Card
Replace
Motherboard
4–5