Dynamic Loading; Capacitive Loading; Closed-Loop Stability; Table 67. Voltage Regulation Limits - Intel SC5650BCDP Technical Product Specification

Intel Server Board S5500BC TPS
®
Parameter
+ 3.3V
+ 5V
+ 12V1,2
- 12V
+ 5VSB

9.2.8 Dynamic Loading

The output voltages should remain within the limits for the step loading and capacitive loading
specified in the following table. The load transient repetition rate should be tested between 50
Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is a test
specification. The  step load may occur anywhere within the MIN load to the MAX load
conditions.
Output
+3.3 V
+5 V
12 V1+12 V2
+5 VSB
Notes:
The +12 V should be tested with 2200 F evenly divided between the four +12 V rails.
1.
2. Step loads on each 12 V output may occur simultaneously.

9.2.9 Capacitive Loading

The power supply should be stable and meet all capacitive loading requirements. The following
table outlines these conditions.
+3.3 V
+5 V
+12 V 1, 2
-12 V
+5 VSB

9.2.10 Closed-Loop Stability

The power supply should be unconditionally stable under all line/load/transient load conditions,
including capacitive load ranges. A minimum of 45° phase margin and -10 dB gain margin is
required. The power supply manufacturer should provide proof of the unit's closed-loop stability
Revision 1.8

Table 67. Voltage Regulation Limits

Tolerance Minimum
- 5% / +5% +3.14
- 5% / +5% +4.75
- 5% / +5% +11.40
- 10% / +10% -10.80
- 5% / +5% +4.75

Table 68. Transient Load Requirements

 Step Load Size
1
6.0 A
4.0 A
18.0 A
0.5 A

Table 69. Capacitive Loading Conditions

Output Minimum
100
10
220 each
1
20
Intel order number: E42249-009
Power and Environmental Specifications
Nominal Maximum
+3.30 +3.46
+5.00 +5.25
+12.00 +12.60
-12.00 -13.08
+5.00 +5.25
Load Slew Rate Test Capacitive Load
250 F
0.25 A/sec
400 F
0.25 A/sec
2200 F 1, 2
0.25 A/sec
20 F
0.25 A/sec
Maximum Units
F
6,800
F
4,700
F
11,000
F
350
F
2000
Units
V
rms
V
rms
V
rms
V
rms
V
rms
109