Voltage Regulation; Dynamic Loading; Table 40. Voltage Regulation Limits; Table 41. Transient Load Requirements - Intel S5000XSL Technical Product Specification

Intel® Server Boards S5000PSL and S5000XSL TPS
8.3.4

Voltage Regulation

The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple / noise.
Parameter
+3.3V
+5V
1
+12V
2
+12V
3
+12V
4
+12V
- 12V
+5VSB
1.
2.
3.
4.
8.3.5

Dynamic Loading

The output voltages shall remain within limits for the step loading and capacitive loading
specified in the table below. The load transient repetition rate shall be tested between 50 Hz
and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test
specification. The Δ step load may occur anywhere within the minimum load to the maximum
load conditions.
Output
+3.3V
+5V
+12V
+5VSB
1.
Revision 1.2

Table 40. Voltage Regulation Limits

Tolerance Minimum
- 5% / +5% +3.14
- 5% / +5% +4.75
- 5% / +5% +11.40
- 5% / +5% +11.40
- 5% / +5% +11.40
- 5% / +5% +11.40
- 5% / +9% - 11.40
- 5% / +5% +4.75
Maximum continuous total output power should not exceed 670 W.
Maximum continuous load on the combined 12 V output shall not exceed 48 A.
Peak load on the combined 12 V output shall not exceed 52 A.
Peak total DC output power should not exceed 730 W.

Table 41. Transient Load Requirements

Δ Step Load Size 1
7.0A
7.0A
25A
0.5A
Step loads on each 12V output may happen simultaneously.
Intel order number: D41763-003
Design and Environmental Specifications
Nominal Maximum
+3.30 +3.46
+5.00 +5.25
+12.00 +12.60
+12.00 +12.60
+12.00 +12.60
+12.00 +12.60
-12.00 -13.08
+5.00 +5.25
Load Slew Rate Test Capacitive Load
4700 μF
0.25 A/μsec
1000 μF
0.25 A/μsec
4700 μF
0.25 A/μsec
20 μF
0.25 A/μsec
Units
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
V
rms
83