Dma I/O Address Map - Lenovo NetVista A40p User Manual

DMA I/O address map

The following table lists resource assignments for the DMA address map. Any
addresses that are not shown are reserved.
Table 2. I/O address map (continued)
Address (hex) Size (bytes)
03F7 (Write) 1
03F7, bit 7 1 bit
03F7, bits 6:0 7 bits
03F8 – 03FF 8
0400 – 047F 128
0480 – 048F 16
0490 – 0CF7 1912
0CF8 – 0CFB 4
0CFC – 0CFF 4
LPTn + 400h 8
OCF9 1
0D00 – FFFF 62207
Table 3. DMA I/O address map
Address Description
(hex)
0000 Channel 0, memory address register
0001 Channel 0, transfer count register
0002 Channel 1, memory address register
0003 Channel 1, transfer count register
0004 Channel 2, memory address register
0005 Channel 2, transfer count register
0006 Channel 3, memory address register
0007 Channel 3, transfer count register
0008 Channels 0–3, read status/write command register
0009 Channels 0–3, write request register
000A Channels 0–3, write single mas register bits
000B Channels 0–3, mode register (write)
000C Channels 0–3, clear byte pointer (write)
000D Channels 0–3, master clear (write)/temp (read)
000E Channels 0-3, clear mask register (write)
000F Channels 0-3, write all mask register bits
0081 Channel 2, page table address register
0082 Channel 3, page table address register
0083 Channel 1, page table address register
0087 Channel 0, page table address register
Description
Diskette channel 1 command
Diskette disk change channel
Primary IDE channel status port
COM1
Available
DMA channel high page registers
Available
PCI configuration address register
PCI configuration data register
ECP port, LPTn base address + hex 400
Turbo and reset control register
Available
Appendix D. System address maps
Bits Byte
pointer
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 15 Yes
00 – 07
00 – 02
00 – 02
00 – 07
A
00 – 07
00 – 03
00 – 03
00 – 07
00 – 07
00 – 07
00 – 07
79