Intel I865PE User Manual page 38

BIOS
DRAM Timing Selectable
For setting DRAM Timing, select By SPD to follow Intel PC DDR SDRAM Serial
Presence Detect Specification.
Options: Manual, By SPD.
CAS Latency Time
This item specifies the number of clock cycles needed after a Column Address Strobe
(CAS) signal before data can be read. The default is by DRAM SPD.
Options: 2, 2.5, 3.
Active to Precharge Delay
This item specifies the number of clock cycles needed after a bank active command
before a precharge can occur (sets the minimum RAS pulse width.). The default is by
DRAM SPD.
Options: 5, 6, 7, 8.
DRAM RAS# to CAS# Delay
This item sets the timing parameters for the system memory such as the CAS (Column
Address Strobe) and RAS (Row Address Strobe). The default is by DRAM SPD.
Options: 2, 3, 4.
DRAM RAS# Precharge
This item refers to the number of cycles required to return data to its original
location to close the bank or the number of cycles required to page memory before
the next bank activate command can be issued. The default is by DRAM SPD.
Options: 2, 3, 4.
Aggressive Memory Mode (AMM)
Aggressive Memory Mode reduces delays within the chipset to improve DDR
DRAM usage efficiency.
Options: Max, Turbo, Expert, Standard.
Performance upgrade using AMM will largely depend on hardware
availability within the chipset.
CPU Bus Park
Options: Auto, Disabled, Enabled.
Intel Fast CS
Options: Auto, Disabled, Enabled.
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