Intel 6 SERIES CHIPSET - SPECIFICATION UPDATE 01-2011 Specification page 15

Errata
8. Incorrect Data for LS or FS USB Periodic IN Transaction
Problem: The Periodic Frame list e ntry in DRAM fo r a USB LS or FS P eriodic IN tr ansaction may
incorrectly get some of its data from a prior Periodic IN transaction which was initiated
very late into the preceding Micro-frame.
It is considered good practice for software to schedule Periodic Transactions at the start
of a Micro-frame. However Periodic transactions may occur late into a Micro-frame due
to the following cases outlined below:
• Asynchronous transaction starting near the end of the proceeding Micro-frame gets
Asynchronously retried
Note: Transactions getting Asynchronous retried would only occur for ill behaved USB device
or USB port with a signal integrity issue
• Or Two Periodic transactions are scheduled by software to occur in the same
Micro-frame and the first needs to push the second Periodic IN transaction to the
end of the Micro-frame boundary
Implication: The implication will be device, driver or operating system specific.
Note: This issue has only been observed in a synthetic test environment
Workaround: None.
Status: No Plan to Fix.
9. HDMI 222 MHz Electrical Compliance Testing Failures
Problem: HDMI 222 M Hz electrical compliance te sting may show ey e diagr am and jitter test
failures on Intel 6 Series Chipsets.
Implication: No functional or visual failures have been observed by Intel. HDMI electrical compliance
failures may be seen at 222 MHz Deep Color Mode. This issue doe s not prevent HDMI
with Deep Color Logo certification as no failures have been seen with 74 .25 MHz Deep
Color Mode (7 20P 60
Specification.
Workaround: None.
Status: No Plan to Fix.
10. SATA Signal Voltage Level Violation
Problem: SATA tr ansmit buffers hav e be en desi gned to maximi ze performa nce and robustness
over a v ariety of routing scenarios. As a result, the S ATA tr ansmit signaling voltage
levels may exceed the maximum motherboard TX connector and device RX connector
voltage specifications as defined in section 7.2.1 of the Serial ATA specification, rev 3.0.
This issue applies to Gen 1 (1.5 Gb/s) and Gen 2 (3.0 Gb/s).
Implication: None known.
Workaround: None.
Status: No Plan to Fix.
11. SATA Differential Return Loss Violations
Problem: The Intel 6 Series Chipset SATA buffer capacitance may be higher than expected.
Implication: There are no know n function al failures. This ma y cause a violation of
compliance test for Receiver or Transmitter Differential Return Loss.
Workaround: None.
Note: Intel has obtained a waiver for the SATA-IO building block status.
Status: No Plan to Fix.
Specification Update
Hz or 108 0P 30 Hz) as req uired HD MI Comp liance T est
the SATA-IO
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