Ic Data - Marantz SR8000 Service Manual

6. IC DATA

Q601:YSS912
SDOB Interface
/CSB
24 * 16
SCK
Sub DSP
SI
SDIB Interface
SDIBSEL
SDOA Interface
24 * 24
OPORT0 7 Main DSP
AC-3/Pro Logic/DTS
SCK
Decoder
SI
SO
/CS
Input Buffer
IPORT0 7
SDIA Interface
SDIASEL
QD01:AD1855
CONTROL DATA
INPUT
VOLUME
MUTE
3
AD1855 SERIAL CONTROL
INTERFACE REFERENCE
83
ATTEN/ MULTIBIT SIGMA-
INTERPOLATOR DELTA MODULATOR
MUTE
16-/18-/20-/24-BIT SERIAL
3
DIGITAL DATA
DATA INPUT INTERFACE
ATTEN/ 83 MULTIBIT SIGMA-
MUTE INTERPOLATOR DELTA MODULATOR
2
SERIAL
MODE
PD/RST MUTE DE-EMPHASIS
1
DGND 28 DVDD
MCLK 2 27 SDATA
CLATCH
3 26 BCLK
CCLK 4 25 L/RCLK
CDATA 5 24 PD/RST
384/256 6
23 MUTE
AD1855
X2MCLK 7 22 ZEROL
TOP VIEW
(Not to Scale)
ZEROR
8 21 IDPM0
DEEMP 9 20 IDPM1
96/48 10 19 FILTB
AGND 11 AVDD
18
OUTR+ 12 17 OUTL+
OUTRÐ OUTLÐ
13 16
FILTR 14 15 AGND
No. NAME I/O FUNCTION
1 VDD1 - +5V power supply (for I/Os)
2 RAMCEN O External SRAM Interface /CE
3 RAMA16 O External SRAM Interface address 16
4 RAMA15 O External SRAM Interface address 15
5 SDIB0 I+ PCM input 0 to Sub DSP
6 SDIB1 I+ PCM input 1 to Sub DSP
7 SDIB2 I+ PCM input 2 to Sub DSP
8 XI I Crystal oscillator connection or input external clock (12.288 MHz)
9 XO o Crystal oscillator connection
10 VSS - Ground
OVFB 11 AVDD - +3.3V power supply (for PLL circuit)
RAMA0 16 12 SDIB3 I+ PCM input 3 to Sub DSP
RAMOEN
13 TEST Test terminal (to be open in normal use)
RAMWEN
14 TEST Test terminal (to be open in normal use)
RAMCEN
15 OVFB O Detection of overflow at Sub DSP
16 DTSDATA O DTS data detection (Refer to "Status Register".)
RAMD0 7
17 AC3DATA O AC-3 data detection (Refer to "Status Register" .)
18 SDOB3 O PCM output from Sub DSP
19 CPO A Output terminal for PLL, to be connected to ground through the external analog filter circuit.
(Refer to "External Circuit for PLL" .)
SDIB3
20 AVSS - Ground (for PLL circuit)
SDIB2
21 VDD2 - +3.3V power supply (for core logic)
SDIB1
SDIB0 22 SDOA2 o PCM output from Main DSP (C, LFE)
23 SDOA1 O PCM output from Main DSP (LS, RS)
SDOA2
24 SDOA0 O PCM output from Main DSP (L, R)
SDOA1
25 RAMA14 O External SRAM Interface address 14
SDOA0
26 RAMA13 O External SRAM Interface address 13
27 RAMA12 O External SRAM Interface address 12
28 RAMA11 O External SRAM Interface address 11
29 RAMA10 O External SRAM Interface address 10
30 VSS - Ground
31 VDD1 - +5V power supply (for I/Os)
32 OPORT0 O Output port for general purpose. (Refer to " OPORT Register")
33 OPORT1 O Output port for general purpose. (Refer to " OPORT Register")
34 OPORT2 O Output port for general purpose. (Refer to " OPORT Register")
35 OPORT3 O Output port for general purpose. (Refer to " OPORT Register")
36 OPORT4 O Output port for general purpose. (Refer to " OPORT Register")
37 OPORT5 O Output port for general purpose. (Refer to " OPORT Register")
38 OPORT6 O Output port for general purpose. (Refer to " OPORT Register")
CPO
39 OPORT7 O Output port for general purpose. (Refer to " OPORT Register")
40 VSS - Ground
XO
41 VDD2 - +3.3V power supply (for core logic)
XI
42 RAMA9 O External SRAM interface address 9
43 RAMA8 O External SRAM interface address 8
44 RAMA7 O External SRAM interface address 7
CRC
45 SDOB2 O PCM output from Sub DSP
46 SDOB1 O PCM output from Sub DSP
47 SDOB0 O PCM output from Sub DSP
48 SDBCK1 I+ Bit clock input for SDOA, SDIB, SDOB. (Refer to " SDOA, SDIB, SDOB Register")
49 SDWCK1 I+ Word clock input for SDOA, SDIB, SDOB. (Refer to " SDOA, SDIB, SDOB Register")
50 VSS - Ground
Pin Input/Output Pin Name
96/48F
CLOCK S
DIGITAL
CLOCK
IN 1 I DGND
SUPPLY
2 2 I MCLK
3 I CLATCH
384/256
VOLTAGE CLOCK
4 I CCLK
CIRCUIT
X2MCLK
5 I CDATA
OUTPUT
DAC
BUFFER
6 I 384/256
ANALOG
OUTPUTS
OUTPUT
DAC
BUFFER
7 I X2MCLK
2 2
8 O ZEROR
ANALOG ZERO
SUPPLY FLAG
9 I DEEMP
10 I 96/ 48
11, 15 I AGND
12 O OUTR+
13 O OUTRÐ
14 O FILTR
16 O OUTLÐ
17 O OUTL+
18 I AVDD
19 O FILTB
20 I IDPM1
21 I IDPM0
22 O ZEROL
23 I MUTE
24 I PD/RST
25 I L /RCLK
26 I BCLK
27 I SDATA
28 I DVDD
47
No. NAME
51 VDD2
52 NONPCM
53
54 MUTE
55 KARAOKE
56 SURENC
57 /SDBCK0
58 RAMA6
59 RAMA5
60
61 RAMA4
62
63 TEST
64 RAMA3
65
66
67
68
69
70 RAMA2
71 VDD1
72 RAMD0
73 RAMD1
74 RAMD2
75 RAMD3
76 RAMD4
77 RAMD5
78 RAMD6
79 RAMD7
80
81 VDD2
82 SDWCK0
83 SDBCK0
84 SDIA0
85 SDIA1
86 RAMA1
87 RAMA0
88 RAMWEN
89 RAMOEN
90
91 VDD2
92 IPORT7
93 IPORT6
94 IPORT5
95 IPORT4
96 IPORT3
97 IPORT2
98 IPORT1
99 IPORT0
100
Description
Digital Ground.
Master Clock Input. Connect to an external clock source at either 256, 384
or 512 F .
S
Latch input for control data. This input is rising-edge sensitive.
Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.
Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel specific attenuation and mute.
Selects the master clock mode as either 384 times the intended sample fre-
quency (HI) or 256 times the intended sample frequency (LO). The state of
this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1855 is in power-down/reset. It must not be changed while the
AD1855 is operational.
Selects internal clock doubler (LO) or internal clock = MCLK (HI).
Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50 m s/15 m s response characteristic on the output
audio spectrum at an assumed 44.1 kHz sample rate.
Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.
Analog Ground.
Right Channel Positive line level analog output.
Right Channel Negative line level analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10 m F and 0.1 m F capacitors to the AGND.
Left Channel Negative line level analog output.
Left Channel Positive line level analog output.
Analog Power Supply. Connect to analog +5 V supply.
Filter Capacitor connection, connect 10 m F capacitor to AGND.
Input serial data port mode control one. With IDPM0, defines one of four
serial modes.
Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.
Left Channel Zero Flag output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.
Power-Down/Reset. The AD1855 is placed in a low power consumption
mode when this pin is held LO. The AD1855 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation.
Left/ Right clock input for input data. Must run continuously.
Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.
Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.
Digital Power Supply Connect to digital +5 V supply.
I/O FUNCTION
- +3.3V power supply (for core logic)
O Detection of non PCM data. (Refer to " Status Register")
CRC O Detection of AC-3 CRC error. (Refer to " Status Register")
O Detection of auto-mute. (Refer to " Status Register")
O Detection of AC-3 karaoke data. (Refer to " Status Register")
O Detection of AC-3 2/0 mode Dolby surround encoded input (Refer to " Status Register")
O Inverted SDBCKO clock output (refer to " Block diagram")
O External SRAM Interface address 6
O External SRAM Interface address 5
VSS - Ground
O External SRAM Interface address 4
/lC Is Initial clear
Test terminal (to be open in normal use)
O External SRAM Interface address 3
/CSB Is+ Sub DSP Chip select
/CS Is Microprocessor interface Chip select
SO Ot Microprocessor interface Serial data output
SI Is Microprocessor interface/Sub DSP Serial data input
SCK Is Microprocessor interface/Sub DSP clock input
O External SRAM Interface address 2
- +5V power supply (for I/Os)
I+/O External SRAM Interface data (STREAM 0 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 1 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 2 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 3 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 4 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 5 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 6 output when External SRAM is not in use)
I+/O External SRAM Interface data (STREAM 7 output when External SRAM is not in use)
VSS - Ground
- +3.3V power supply (for core logic)
I Word clock input for SDIA, SDOA, SDIB, SDOB (Refer to " SDIA, SDOA, SDIB, SDOB Register")
I Bit clock input for SDIA SDOA SDIB SDOB (Refer to " SDIA, SDOA, SDIB, SDOB Register")
I AC-3/DTS bitstream (or PCM) data input for Main DSP (Refer to " SDIA Register")
I AC-3/DTS bitstream (or PCM) data input for Main DSP (Refer to " SDIA Register")
O External SRAM Interface address 1
O External SRAM Interface address 0
O External SRAM Interface /WE
O External SRAM Interface /OE
VSS - Ground
- +3.3V power supply (for core logic)
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
I+ Input port for general purpose (Refer to " IPORT Register")
VSS Ground
Note ) Is : Schmidt trigger input terminal
I+ : Input terminal with a pull-up resistor
O : Digital output terminal
Ot : Tri-state digital output terminal
A : Analog terminal
Q351:LC72722
48