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6. IC DATA
QE09:PM4007A
QPSK input
CPIN
CMIN
DOUT
DOUTB
PDDIS
46.08MHz
oscillator
46.08MHz
PDO
LPF
comparator
VI
VCXO
18.432 MHz
VO
RESET
OSCON
No. Name
I/O
Function
1
GND
-
GND
2
VDD
-
+5VD
3 RESET
I
System Reset
At "L" reset
4 OSCON
I
Oscillator control
At"H" during normal operation At "L" during standby
5
DATA
I
TEST
6
MCK
I
TEST
7
MLTB
I
TEST
8
IDST
O
TEST
9
IDCK
O
TEST
10
IDO
O
TEST
11
TM0
I
TEST
12 ECCK
O
TEST
13
DEN
O
TEST
14
DRY
O
TEST
15 MSYC
O
TEST
16
TM1
I
TEST
17
A0
O
RAM A0
18
A1
O
RAM A1
19
A2
O
RAM A2
20
A3
O
RAM A3
21
A4
O
RAM A4
22
A5
O
RAM A5
23
TM2
I
TEST
24
TM3
I
TEST
25 XOUT
O
TEST
26
XIN
I
TEST
27 XEXT
I
TEST
28
GND
-
GND
29
VDD
-
+5VD
30
A6
O
RAM A6
31
A7
O
RAM A7
32
GND
-
GND
33
VDD
-
+5VD
34
A12
O
RAM A12
35
A14
O
RAM A14
36
WEB
O
RAM WEB
37
A13
O
RAM A13
38
A8
O
RAM A8
39
A9
O
RAM A9
40
GND
-
GND
41
A11
O
RAM A11
42
OEB
O
RAM OE
43
A10
O
RAM A10
44
DB7
B
RAM D7
45
DB6
B
RAM D6
46
DB5
B
RAM D5
47
DB4
B
RAM D4
48
DB3
B
RAM D3
49
DB2
B
RAM D2
50
DB1
B
RAM D1
QU02:NJU3711
DATA
8
12 P1
13
9
1
CLK
2
V
4
3
SS
5
6
V
DD
14
7
STB
10
CONTROL CIRCUIT
NJU3711
11
CLR
SYNC
Detection-
S/P
Demoduration
Safeguard
A (14:0)
Address
DB(7:0)
OEB
Timing
WEB
C2F1
Phase
C2F0
9KHz
Error
correction
C1F1
C1F0
1/2048
DAI
MUTO
9.216KHz
divider
control
1/2
SW
DAOUT
Serial data stream output
C9M
MUTI
DAIN
No. Name
I/O
Function
51
DB0
B
RAM D0
52
VDD
-
+5VD
53
GND
-
GND
54
TI1
I
TEST
55
VIN
I
VCXO input
56 VOUT
O
VCXO output
57
TI2
I
TEST
58
TI3
I
TEST
59 TLDB
I
TEST
60
TCK
I
TEST
61
TRP
O
TEST
62
TDO
O
TEST
63
PDO
O
Phase comparator output (3-state)
64
TI4
I
TEST
65 PDDIS
I
Control input for PDO out
At "L" Output ON
66 MUTO
O
Muting output. Mutes at "H".
Sets to "H" when MUTI = H or the AC-3 period cnanot be received.
67
TI5
I
TEST
68 VLDY
O
TEST
69 DASYO
O
TEST
70 DAOUT
O
Digital OUT (serial data stream output)
71
DAIN
I
Digital external input : Sets to DAOUT when DASEL is at "H"
72 DASEL
I
Selects digital OUT
73
TI8
I
TEST
74
C2F1
O
N.C.
75
C2F0
O
N.C.
76
C1F1
O
N.C.
77
C1F0
O
Displays C1 correction error status. Outputs error count at C1.
78
MUTI
I
Muting input. Mutes at "H".
79
VDD
-
+5VD
80
GND
-
GND
81 AVDD
1
+5VD
82
CPIN
I
Analog converter inverted input
83 CMIN
I
Analog converter inverted input
84 AGND
-
GND
85
TM4
I
TEST
86
VDD
-
+5VD
87
DIN
I
TEST
88 DOUT
O
Analog converter inverted output
89 DOUTB
O
Analog converter inverted reverse output
90
C9M
O
N.C.
91
GND
-
GND
92 WINGT
O
TEST
93 SYST0
O
TEST
94 SYST1
O
TEST
95 ADST0
O
TEST
96 ADST1
O
TEST
97
TM5
I
TEST
98 BUNRI
I
TEST
99 AGND
-
GND
100 AVDD
-
+5VD
QM07:NJU3713D
DATA
10
11
CLK
P2
P3
V
5
SS
P4
P5
18
V
DD
P6
P7
P8
12
STB
CONTROL CIRCUIT
NJU3713
CLR
13
51
QD01-QD03,QD41-QD43:AD1855
SRAM
32K x 8
AD1852
16-/18-/20-/24-BIT
ATTEN/
DIGITAL
MUTE
DATA INPUT
SERIAL
DATA
INTERFACE
SERIAL
2
ATTEN/
MODE
MUTE
RESET
Pin
In/Out
1
I
2
I
3
I
4
I
5
I
6
7
I
8
O
9
I
10
I
11, 15
I
12
O
13
O
14
O
16
O
17
O
18
I
19
20
I
21
I
22
O
23
I
24
I
25
I
26
I
27
I
28
I
IDPM1 (Pin 20)
0
0
1
1
QL07:NJU3718
15
DATA
16
CLK
14 P1
15
P2
16
P3
17
P4
1
P5
2
P6
3
P7
4
P8
6
P9
V
SS
21
7
P10
V
28
8
P11
DD
9
P12
17
STB
CONTROL CIRCUIT
CLR
18
DIGITAL
CLOCK
CONTROL DATA
SUPPLY
IN
INPUT
VOLUME
MUTE
2
3
SERIAL CONTROL
VOLTAGE
AUTO-CLOCK
INTERFACE
REFERENCE
DIVIDE CIRCUIT
8 x F
MULTIBIT SIGMA-
S
DAC
INTERPOLATOR
DELTA MODULATOR
ANALOG
OUTPUTS
8 x F
MULTIBIT SIGMA-
S
DAC
DELTA MODULATOR
INTERPOLATION
2
2
MUTE
DE-EMPHASIS
ANALOG
ZERO
SUPPLY
FLAG
Pin Name
Description
DGND
Digital Ground.
MCLK
Master Clock Input. Connect to an external clock source at either 256 F
, 384 F
,
S
S
512 F
, 768 F
, or 1024 F
.
S
S
S
CLATCH
L atch Input for Control Data. This input is rising-edge sensitive.
CCLK
Control Clock Input for Control Data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
CDATA
Serial Control Input, MSB first, containing 16 bits of unsigned data per channel. Used
for specifying channel-specific attenuation and mute.
N C
N o Connect.
192/48
Selects 48 kHz (LO) or 192 kHz Sample Frequency.
ZEROR
Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal
input for more than 1024 LR Clock Cycles.
DEEMP
De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used
to impose a 50µs/15µs response characteristic on the output audio spectrum at an
assumed 44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be
selected via SPI control register.
96/48
Selects 48 kHz (LO) or 96 kHz Sample Frequency.
AGND
Analog Ground.
OUTR+
Right Channel Positive Line Level Analog Output.
OUTRÐ
Right Channel Negative Line Level Analog Output.
FILTR
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-
ence with parallel 10µ F and 0.1µ F capacitors to the AGND.
OUTLÐ
L eft Channel Negative Line Level Analog Output.
OUTL+
Left Channel Positive Line Level Analog Output.
AVDD
Analog Power Supply. Connect to Analog 5 V Supply.
FILTB
Filter Capacitor Connection. Connect 10µ F capacitor to AGND (Pin 15).
IDPM1
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
IDPM0
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
ZEROL
Left Channel Zero Flag Output. This pin goes HI when Left Channel has no signal
input for more than 1024 LR Clock Cycles.
MUTE
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.
RESET
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port
registers are reset to the default values. Connect HI for normal operation.
L /RCLK
Left/ Right Clock Input for Input Data. Must run continuously.
BCLK
Bit Clock Input for Input Data. Need not run continuously; may be gated or used in a
burst fashion.
SDATA
Serial Input, MSB first, containing two channels of 16, 18, 20, and 24 bits of twos
complement data per channel.
DVDD
Digital Power Supply Connect to digital 5 V supply.
Table I. Serial Data Input Mode
IDPM0 (Pin 21)
Serial Data Input Format
0
Right-Justified
2
1
I
S-Compatible
0
Left-Justified
1
DSP
Q351:LC72720
19 P1
20
P2
22
P3
23
P4
24
P5
25
P6
26 P7
27
P8
1
P9
2
P10
3
P11
4
P12
P13
5
6
P14
8
P15
9
P16
10 P17
11
P18
12
P19
13
P20
14
SO
NJU3718
52
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