Integrated Peripherals - JETWAY 615TCFR3A User Manual

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2 and 3.
SDRAM Cycle Time Tras/Trc
Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.
SDRAM RAS-to-CAS Delay
This field let's you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2 and 3.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2 and 3.

3-7 Integrated Peripherals

CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
On-Chip IDE Function
On-Chip SIO Function
On-Chip Device Function
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F5:Previous Values
On-Chip IDE Function
Please refer to section 3-7-1
On-Chip SIO Function
Please refer to section 3-7-2
On-Chip Device Function
Integrated Peripherals
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F6:Optimized Defaults
33
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