Advanced Chipset Features - TYAN TRINITY 450 Manual

3.4 Advanced Chipset Features

This section describes the settings for the chipset installed on this motherboard. Please note that the
parameters described in this section are for technically competent users only. Do not change
these values unless you completely understand the consequences of your changes.
Bank 0/1 to
Bank 6/7 DRAM Timing
SDRAM Cycle Length
DRAM Drive Strength
DRAM Drive Value
Memory Hole
P2C/C2P Concurrency
System Bios Cacheable
Video RAM Cacheable
AGP Aperture Size
AGP-4x Mode
AGP Driving Control
AGP Driving Value
AGP Fast Write
OnChip USB
USB Keyboard Support
CPU to PCI Write Buffer
PCI Dynamic Buffering
(continued on next page)
32
Settings depend on type of memory installed, and therefore
these settings are reserved. [Default settings are 5/10ns]
Sets the CAS latency timing. [Default setting is 3]
Reserved. [Default is Auto]
Reserved. [Default is 2F]
Specifies the location of an area or memory that cannot be
addressed on the ISA bus. [Default is Disabled]
If Enabled, the PCI/AGP Master to CPU cycle can be concurrent
if the Host CPU is performing R/W access to the PCI or slave
devices. [Default is Enabled]
Sets ability to cache system BIOS ROM at F0000h-FFFFFh.
[Default is Disabled]
Sets whether the video memory should be cacheable. [Default is
Disabled]
The aperture is a portion of the PCI memory address range ded-
icated for graphics memory address space. [Default is 64M]
Enables the 4X AGP mode (requires a 4X-capable AGP card).
[Default is Enabled]
Some AGP cards require setting this option, otherwise this
option is reserved. [Default is Auto]
This function is generally reserved for manufacturer use.
[Default is dependent on graphics card]
Setting is dependent on AGP card. [Default is Disabled]
Sets whether you have USB devices. [Default is Enabled]
Enable or disable use of a USB keyboard. [Default is Disabled]
Setting this can compensate for speed differences between the
CPU and PCI bus. [Default is Enabled]
If Enabled, every write transaction goes to write buffer. Burstable
transactions then burst on the PCI bus, but non-burstable trans-
actions do not. [Default is Enabled]
http://www.tyan.com