Signal Definitions - Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet

Signal Definitions

5

Signal Definitions

5.1 Signal Definitions
Table 5-1. Signal Definitions (Sheet 1 of 8)
Name
A[37:3]#
A20M#
ADS#
ADSTB[1:0]#
AP[1:0]#
Type
I/O A[37:3]# (Address) define a 2
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins of all agents on the FSB. A[37:3]# are protected by
parity signals AP[1:0]#. A[37:3]# are source synchronous signals
and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors
sample a subset of the A[37:3]# lands to determine their power-on
configuration. See Section
I If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wrap-
around at the 1 MB boundary. Assertion of A20M# is only supported
in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an I/O write instruction, it must be valid along
with the TRDY# assertion of the corresponding I/O write bus
transaction.
I/O ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[37:3]# lands. All bus agents observe
the ADS# activation to begin parity checking, protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must be
connected to the appropriate pins on all Quad-Core Intel® Xeon®
Processor 5400 Series FSB agents.
I/O Address strobes are used to latch A[37:3]# and REQ[4:0]# on their
rising and falling edge. Strobes are associated with signals as shown
below.
Signals
REQ[4:0]#, A[16:3]#,
A[37:36]#
A[35:17]#
I/O AP[1:0]# (Address Parity) are driven by the request initiator along
with ADS#, A[37:3]#, and the transaction type on the REQ[4:0]#
signals. A correct parity signal is high if an even number of covered
signals are low and low if an odd number of covered signals are low.
This allows parity to be high when all the covered signals are high.
AP[1:0]# must be connected to the appropriate pins of all Quad-Core
Intel® Xeon® Processor 5400 Series FSB agents. The following table
defines the coverage model of these signals.
Request Signals
A[37:24]#
A[23:3]#
REQ[4:0]#
Description
38
-byte physical memory address
7.1.
Associated Strobes
ADSTB0#
ADSTB1#
Subphase 1 Subphase 2
AP0# AP1#
AP1# AP0#
AP1# AP0#
Notes
3
2
3
3
3
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