Intel E5410 - Cpu Xeon Quad Core 2.33Ghz Fsb1333Mhz 12M Lga771 Tray Datasheet page 77

Signal Definitions
Table 5-1. Signal Definitions (Sheet 7 of 8)
Name
RSP#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI[12:10]
TESTIN1
TESTIN2
THERMTRIP#
Type
I RSP# (Response Parity) is driven by the response agent (the agent
responsible for completion of the current transaction) during
assertion of RS[2:0]#, the signals for which RSP# provides parity
protection. It must connect to the appropriate pins of all processor
FSB agents.
A correct parity signal is high if an even number of covered signals
are low and low if an odd number of covered signals are low. While
RS[2:0]# = 000, RSP# is also high, since this indicates it is not being
driven by any agent guaranteeing correct parity.
O SKTOCC# (Socket occupied) will be pulled to ground by the processor
to indicate that the processor is present. There is no connection to
the processor silicon for this signal.
I SMI# (System Management Interrupt) is asserted asynchronously by
system logic. On accepting a System Management Interrupt,
processors save the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the deassertion of RESET# the processor
will tri-state its outputs. See
I STPCLK# (Stop Clock), when asserted, causes processors to enter a
low power Stop-Grant state. The processor issues a Stop-Grant
Acknowledge transaction, and stops providing internal clock signals
to all processor core units except the FSB and APIC units. The
processor continues to snoop bus transactions and service interrupts
while in Stop-Grant state. When STPCLK# is deasserted, the
processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
I TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
I TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
O TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification support.
I TESTHI[12:10] must be connected to a V
resistor for proper processor operation. Refer to
TESTHI grouping restrictions.
I TESTIN1 must be connected to a VTT power source through a resistor
as well as to the TESTIN2 land of the same socket for proper
I
processor operation.
TESTIN2 must be connected to a VTT power source through a resistor
as well as to the TESTIN1 land of the same socket for proper
processor operation.
O Assertion of THERMTRIP# (Thermal Trip) indicates the processor
junction temperature has reached a temperature beyond which
permanent silicon damage may occur. Measurement of the
temperature is accomplished through an internal thermal sensor.
Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the
processor junction temperature. To protect the processor its core
voltage (V ) must be removed following the assertion of
CC
THERMTRIP#. Intel also recommends the removal of V
THERMTRIP# is asserted.
Driving of the THERMTRIP# signals is enabled within 10 μs of the
assertion of PWRGOOD and is disabled on de-assertion of PWRGOOD.
Once activated, THERMTRIP# remains latched until PWRGOOD is de-
asserted. While the de-assertion of the PWRGOOD signal will de-
assert THERMTRIP#, if the processor's junction temperature remains
at or above the trip level, THERMTRIP# will again be asserted within
10 μs of the assertion of PWRGOOD.
Description
Section 7.1.
power source through a
TT
Section 2.6
when
TT
Notes
3
2
2
for
1
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