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Subtract
SUR
3F
RR
Rl,R2
FP.
Subtract opr 2 from opr
1
Spec
0
Result
Unnormalized (Short)
(FPR)
(FPR)
Sign
Fract
=
0
(Low-order FPRs ignored and unchanged)
Exp Oflo
1
Result
<
0
2 Result
>
0
3
Exp Oflo
Supervisor Call
SVC
OA
RR
I
Immediate bits (8-15) replace (24-31) of the
None
Unchanged
old PSW which is stored as a result of the
interrupt.
(16-23) are made zero.
(Old PSW at loc 32)
(New PSW from loc 96)
Test and Set
TS
93
sr-i
ni(Bi)
Hi-order bit of 1st opnd adr sets cond code.
Prot
0
Hi-order
Entire byte then set to 1 's
Adr
bit= 0
1 Hi-order
bit= 1
2
---
3
---
Test Channel
TCH
9F
SI
Dl(Bl)
Opr
1
(21-23) identifies the tested channel.
Privileged
0
Chan Avl
(Bits 24-31 are ignored.)
Oper
1 Int Pending
(Instruction checks the channel's status
2
Chan in
and sets appropriate cond code. )
Burst Mode
3
Chan not
Operational
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