Motorola V200 Service Manual page 13

Level 3 Service Manual
6881039B10
1.2288Mb/sec CDMA data stream. This stream is then converted to analog signals
and sent to RF transceiver IC U700 as TXIP, TXIM, TXQP, and TXQM.
Keyboard Interface
The keypad interface consists of 7 8-row and 2 3-column input pins.
The keypad port generates a CPU interrupt any time a key press is detected. This
interrupt is capable of taking the processor out of low power mode.
For each key press, 2 GPIO will be asserted. At least 1 of the 2 GPIO will be an
interruptible ROW control line. The key is derived from the interrupt and the
identification of the 2 control lines that are pulled low.
Glitch suppression circuit qualifies the keypad input to prevent noise from inad-
vertently interrupting the CPU.
The circuit is a 4-state synchronizer clocked at 32kHz. An interrupt is not generated
until all 4 synchronizer stages have latched a valid key assertion, effectively
filtering out any noise less 122 us in duration. The debounce time is about 32 ms.
Figure 3 is a simplified diagram of the keypad logic.
Figure 3. V200 keypad logic
The keys on the PCB use a three contact design. One of the contacts is tied to ground
while the other two are pulled high (2.7 V) and connected to the rows and columns
inputs. When a key is pressed, all three of its pads are shorted and therefore
grounded. Each key is uniquely distinguished by the two lines pulled low. No
strobing of the keypad is necessary.
October 04, 2001
Circuit Description
010994o
9