A/D Converter; Signal Polarity; System Interface Logic; Control Interface - Lexicon 960L Service Manual

960L Multi-Channel Digital Effects System Service Manual
With a full-scale signal, the allowable additional input common-mode voltage range is at least +18dBu (+/-
8.7Vpeak), limited by the clipping level of U20. Unwanted hum and noise at the input are unlikely to reach
such high levels, but for a single-ended input, half the signal is common mode at this level.

A/D Converter

A/D converter U4 (AK5393) is powered on its VD pin by the main 5VD system power from the backplane,
and on its VA pin by higher-quality 5VA regulated on-board by U3. Power is decoupled by ferrites FB3, FB4
and bypassed by C10, 11,12,13.
The channel 1 analog input is applied to the left stereo input AINL. The associated internally-developed
reference voltages VREFL and VCOML are filtered by C37, 51,27.
U4 operates its serial digital audio port in I2S mode, SMODE[2:1]=1,0. U4 receives I2S framing and bitclock
ADLRCK/ and ADSCK12/ from interface fpga U1 (sheet 4) and delivers two channels of 24-bit serial digital
audio back into U1. AD12_SDO carries channel 1 and 2 data as left and right, respectively. Master clocks
to the four A/D chips are distributed on separate lines from one pin of U1. MCK12 connects to U4, the
converter for channels 1 and 2. Two A/D logic inputs are under the control of host software, via the U1
interface. CONV_RESET/ and DFS0 are applied to all four A/D chips in parallel. DFS1, connected to the
TEST pins, is grounded by 0-ohm jumper R1.

Signal Polarity

There are no inversions in the analog signal path, so a positive voltage between J2.2 and J2.3 appears as a
positive differential signal between AINL+ and AINL- and produces a positive digital value fed into the
system via interface U1.

System Interface Logic

Fpga U1 (Xilinx XCS05, sheet 5) is the interface between the I/O backplane control, data(host and audio),
and clock buses and the A/D converters and their associated controls. When power is applied to the card,
the FPGA automatically receives its internal configuration from companion SROM U2. Configuration takes a
few tens of msec, after which the onboard logic assumes its default state and is ready to be
interrogated/programmed by system software.

Control Interface

The Analog Input card appears as two, byte-wide ports on the I/O backplane databus IOBUS_DATA[7:0], at
the addresses determined by the decoding of SLOT_SEL/ and one address bit, IOBUS_ADDR0.
IOBUS_WR/RD determines the direction of data transfer (low=write, high=read), with IOBUS_DS/ being
asserted low during data transfers. U1 captures write data on the rising edge of IOBUS_DS/. Two pins of
the FPGA are control outputs whose states get programmed from the host computer. CONV_RESET/ and
DFS0 control all the A/D converters in parallel. DFS1 is permanently grounded as described above.
IOBUS_RESET/ and PWROK are used to initialize various internal FPGA state. When low, ALL_MUTE/
forces the octal audio data lines(TMIX1_SERD0,1,2,3,10,11) to zero.

Register Descriptions

OFFSET NAME Access Default
ADDR
0x00 IDREG(7:0 RO
)
IDREG(7:4) RO
IDREG(3:0) RO
0x01 CTLREG(7:0)
CTLREG(7:6) RW
CTLREG(5) RW
7-16
Description
Value
0x11 Board ID register
1 Type(1=AIN)
1 Interface revision number
0X3 TMIX1 output serial octal drive select.
00 Drives TMIX1_SERD0/TMIX1_SERD1 octal pair
01 Drives TMIX1_SERD2/TMIX1_SERD3 octal pair
10 Drives TMIX1_SERD10/TMIX1_SERD11 octal pair
11 AIN Octals are not driven(all drivers are tristated)
0 AKM5394EN : This enables the DFS1 driver for use with the AKM5394.