Circuit Description; Startup Sequence; Aes Card Memory Map - Lexicon 960L Service Manual

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Circuit Description

This section is a page by page description of the 960L AES card schematic.
Crystal RX/TX Devices (sheets 1-4)
Sheet 1 of the schematic shows a single Crystal receiver and transmitter and associated support circuitry.
Sheets 2, 3, and 4 are the other receivers and transmitters. The description of sheet 1 also applies to
sheets 2, 3, and 4. Digital audio is received through an XLR connector (J3). This differential pair is
transformer coupled by TX2 and terminated by R38 before being presented to the Crystal CS8413 digital
audio receiver (U6). The device has a microprocessor interface and internal registers that are used to
configure the device and to monitor the status of incoming digital audio stream. Digital audio is transmitted
by the Crystal CS8403A digital audio transmitter (U10). This device also has a microprocessor interface
and internal registers that are used to configure the device. The differential output from this device is
transformer coupled through TX10 and transmitted through an XLR connector (J7).
FPGA (sheet 5)
The primary function of the AES FPGA (U2) is to convert octal format serial audio to I2S format in the
following manner. The Crystal receivers pass I2S audio to the AES FPGA that packs the eight samples into
octal serial streams that interface to the Reverb Card via the I/O Bus. The Crystal transmitters receive I2S
audio from the FPGA. These I2S streams are unpacked from octal serial streams that are sent from the
Reverb Card. The FPGA also contains control and status registers to set up and monitor the card's
operation. These registers are described in sections 5 – 10 of this document. At start-up the FPGA clocks in
its configuration program from a serial PROM (U3).
I/O Bus Buffers (sheet 6)
The buffers to interface the AES card to the I/O Bus are shown on sheet 6.
I/O Bus Connector (sheet 7)
The I/O Bus connector (J1) is a 96 pin Euro DIN connector that is used to interface the AES card to the
Reverb Card.
Bypass Caps and Ground Jumpers (sheet 8)
The chassis ground - signal ground jumpers shown on sheet 8 should be installed to connect chassis
ground to signal at the AES card to meet EMC requirements.

Startup Sequence

At power-up the AES FPGA clocks in serial configuration data from its companion SPROM. This program is
used by the FPGA to configure its internal gates and memory to perform the desired functions for the AES
card. After the FPGA has successfully configured itself it illuminates the DONE LED (D1, sheet 6). The AES
card is now ready to respond to a request from the Reverb Card to identify itself. This process consists of
the Reverb Card reading the configuration register in the AES FPGA, which is set a value of 32 hex. This
tells the Reverb Card that this is an AES card in this slot on the I/O bus, and the Reverb Card then
programs the FPGA registers and the registers in the Crystal devices for card to operate. The AES card is
accessed periodically by software during normal operation to poll the status of the incoming AES audio/data
streams for errors, and the Reverb Card also accesses the AES card registers to perform the sequence
required when locking the 960L sample clock to an AES input. The sequence is described in section 7 of
this document.

AES card Memory Map

Address Resource
7-29