Switch Settings (Ni 781Xr/783Xr Only) - National Instruments PXI-7811 User Manual

PXI_Star*
Lbl0
Lbl1
Lbl2
Lbl3
Slot 2
1
* A Slot 2 device ties the PXI_Star Line to the PXI 10 MHz clock
1 Shared Local Bus Lines between Slot 2 and Slot 3
2 Shared Trigger Lines between Slot 2, Slot 3, and Slot 4
3 Shared Local Bus Lines between Slot 3 and Slot 4
Refer to the PXI Hardware Specification Revision 2.1 and PXI Software
Specification Revision 2.1 at
PXI triggers.

Switch Settings (NI 781xR/783xR Only)

Refer to Figure 2-13 for the location of switches on the NI PCI-781xR and
Figure 2-14 for the location of switches on the NI PXI-781xR. Refer
to Figure 2-15 for the location of switches on the NI PCI-783xR and
Figure 2-16 for the location of switches on the NI PXI-783xR. For normal
operation, SW1 is in the OFF position. To prevent a VI stored in Flash
memory from loading to the FPGA at power up, move SW1 to the
ON position, as shown in Figure 2-17.
SW2 and SW3 are not connected.
Note
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PXI_Star
Lbr0 Lbl0
Lbr1 Lbl1
Lbr2 Lbl2
Lbl3
Lbr3
Slot 3
Figure 2-12. PXI Star Trigger Connections in a PXI Chassis
www.pxisa.org
2-23
Chapter 2 Hardware Overview of the NI 78xxR
PXI_Star
Lbr0 Lbl0
Lbr1 Lbl1
Lbr2 Lbl2
Lbr3 Lbl3
Slot 4
for more information about
R Series Multifunction RIO User Manual
2
Lbr0
Lbr1
Lbr2
Lbr3
3