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(4)
Address Decoder
and Memory Map
The CPU can access a 64K byte memory area. The merAory
area
is divided
into
one
32K
byte, and two
16K
byte blocks
by IC104
using two address signals (A 14, A 15)
.
Each of the three
blocks
are
tied
to the
ROM,
RAM and 1/0 areas.
The
RAM area
is
divided into SK byte by
IC104
using one address
sig
nal
(A 13).
By IC104
,
1 /0
area is
divided
into 4K byte
blocks.
The CPU can access the 1/0, when
the
two address signals (A 14, A 15) are both
L
leve
ls
.
At this
time
the ROM and the RAM are disabled.
KX-W50TH Memory and
1
/0
map
Address
Chip
Description
0000
(Internal
Register)
32 byte
001F
0020
Not used
003F
0040
(Internal
RAM)
192 byte
00FF
0100
Not
used
0FFF
1000
IC104
1
/0
(Data
Lat
ch
(30 bits))
1FFF
2000
IC104
1/0
(Key
input)
2FFF
3000
IC104
1
/0 (LCD Display)
3FFF
4000
RAM
(IC103)
2K byte
5FFF
6000
Not used
7FFF
8000
ROM (IC102)
32K byte
FFFF
KX-W60TH Memory and
1
/0
map
Address
Chip
Description
0000
(Internal
Register)
32 byte
001F
0020
Not used
003F
0040
(Internal RAM)
192 byte
00FF
0100
Not used
0FFF
1000
1/0 (Data Latch
(30
bits))
1FFF
IC104
2000
1/0 (Key input)
2FFF
IC104
3000
3FFF
IC104
1
/0 (LCD Display)
4000
RAM
(IC
301)
8K byte
5FFF
6000
Expansion
RAM
(IC302)
8K
byte (option)
7FFF
8000
ROM
(IC102)
32K
byte
FFFF
·-
10.2.4 Interface Circuit
The interface
circuit
handles the
handshaking
needed
for
communica tion with a
I/
F Adaptor
(RP-K100).
The
RP-K100 allows
interfacing
w ith a
host
compute
r.
The
handshake method is described in the following steps.
Process;
(1) The
RP
-K100
changes the ON
LINE
signal from H to
L
indicating that data transmission has started
.
T
his
ON LINE signal remains Low during
the
transmission of
1
byte.
(2)
Th
e
RP-K100
first
sends
the
LSB
(DO)
of a
transmitted
byte
to the
TXD line and changes the STB
signa
l
from H to L. This STB
signal
is sent to
P51
of the CPU wh ich is the interruption.
(3)
In
the interruption state, the CPU receives a
T
XD signal
and changes the ACK signal from
L
to
H.
This
ACK
signa
l
is
sent to the RP-K100.
(4)
After the RP-K100 has
received the
ACK signal (L level),
the
STB signal changes from
L
to
H.
(5)
When the STB signal (High) is sent from the
RP-K100,
the thermalwriter sends the ACK signal
(High)
to the RP-K100.
(6) When the ACK signal is High, the RP-K100 starts to send the next bit of data
.
(7) Once the RP-K100 sends
1
byte
of data (8 bits) to the CPU
,
the ON LINE signal changes from L to
H.
Circuit Diagram
I/
F ADAPTOR
INTERFACE
,---------
------
---
7
I
I
I
I
'
1
(
ON
LINE
,
I
I
' 2
(
STB
,
(
ACK
'
3
(
TXD
'
4
,
(
NC
)
(CN202)
(
NC
)
(J2]
(
NC
)
r,::::
'2.-
(
NC
)
'2
'x
I(
GND
}
9
~
n
/"'
~
CN201
1-r-
~
L_
-
--------
--------
--'
(CN114)
[J2]
+5V
Z104
r---7
I
I
I
I
I
I
L_
IC10
1
CPU
~--------..,___+-~--~
2 ~ 3 ~P56
~---------~~---
1
.!.:
8 ~P51
~-----_._---~
2 ~ 4
P57
.-----
-
- 1 6
--1
P27
0101
(
)=KX-WSOTH
[
]
=
KX-W60TH
-
28
-
-
29
-
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