Sony UDA-1 Service Manual page 59

DIGITAL BOARD IC402 ADSP-21488KSWZ-3A1 (DSP)
Pin No. Pin Name
1 VDD_INT
2 CLK_CFG1
3 BOOT_CFG0
4 VDD_EXT
5 VDD_INT
6 BOOT_CFG1
7 GND
8, 9 NC
10 CLK_CFG0
11 VDD_INT
12 CLKIN
13 XTAL
14 VDD_EXT
15, 16 VDD_INT
17 XRESETOUT
18 VDD_INT
19 DPI_P01
20 DPI_P02
21 DPI_P03
22 VDD_INT
23 DPI_P05
24 DPI_P04
25 DPI_P06
26 VDD_EXT
27, 28 DPI_P08, DPI_P07
29 VDD_INT
30 to 34 DPI_P09 to DPI_P13
35 DAI_P03
36 DAI_P14
37 to 39 VDD_INT
40 DAI_P13
41 DAI_P07
DAI_P19, DAI_P01,
42 to 44
DAI_P02
45 VDD_INT
46 VDD_EXT
47 VDD_INT
48 DAI_P06
49 DAI_P05
50 DAI_P09
51 DAI_P10
52 VDD_INT
53 VDD_EXT
54 DAI_P20
55 VDD_INT
56 DAI_P08
57 DAI_P04
58 DAI_P14
59 DAI_P18
60 DAI_P17
61 DAI_P16
62 DAI_P15
63 DAI_P12
64 VDD_INT
65 DAI_P11
66, 67 VDD_INT
68 GND
I/O
- Power supply terminal (+1.1V) (for core)
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
I
Fixed at "H" in this unit
I Boot mode selection signal input terminal
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I Boot mode selection signal input terminal
- Ground terminal
- Not used
Core instruction rate to CLKIN (pin 12) ratio selection signal input terminal
I
Fixed at "L" in this unit
- Power supply terminal (+1.1V) (for core)
I System clock input terminal (10 MHz)
O System clock output terminal (10 MHz)
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I/O Reset signal output and running reset signal input terminal
- Power supply terminal (+1.1V) (for core)
I Serial data input from the system controller
O Serial data output to the system controller
I Serial data transfer clock signal input from the system controller
- Power supply terminal (+1.1V) (for core)
I/O Not used
I Chip enable signal input from the system controller
I/O Not used
- Power supply terminal (+3.3V) (for I/O)
I/O Not used
- Power supply terminal (+1.1V) (for core)
I/O Not used
I/O Not used
I Muting signal input terminal
- Power supply terminal (+1.1V) (for core)
O L/R sampling clock signal output to the D/A converter
O DSD serial data output to the D/A converter
I/O Not used
- Power supply terminal (+1.1V) (for core)
- Power supply terminal (+3.3V) (for I/O)
- Power supply terminal (+1.1V) (for core)
I/O Not used
O Serial data output to the D/A converter
O FS rate capture signal output to the system controller
I Bit clock signal input from the digital audio interface receiver
- Power supply terminal (+1.1V) (for core)
- Power supply terminal (+3.3V) (for I/O)
I L/R sampling clock signal input from the digital audio interface receiver
- Power supply terminal (+1.1V) (for core)
I Serial data input from the digital audio interface receiver
I/O Not used
I DSD L channel serial data input from the USB audio processor
I DSD R channel serial data input from the USB audio processor
I Master clock signal input from the clock selector
I DSD serial clock signal input from the USB audio processor
I I2S L/R sampling clock signal input from the USB audio processor
I/O Not used
- Power supply terminal (+1.1V) (for core)
I Interrupt request signal input from the FLAG2 (pin 82)
- Power supply terminal (+1.1V) (for core)
- Ground terminal
Description
Fixed at "L" in this unit
Fixed at "L" in this unit
"L": Muting
UDA-1
Not used
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