Counter N Gate Signal - National Instruments NI 6608 User Manual

Counter n Gate Signal

Parameter
Tgatepw
For buffered measurements, the minimum period required for the CtrnGate signal is
Note
determined by how fast the system can transfer data from your device to computer memory.
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You can select any PFI or RTSI, as well as many other internal signals like
the Counter n Gate (CtrnGate) signal. The CtrnGate signal is configured in
edge-detection or level-detection mode depending on the application
performed by the counter. The gate signal can perform many different
operations including starting and stopping the counter, generating
interrupts, and saving the counter contents.
You can export the CtrnGate signal to the I/O connector's default PFI input
for each CtrnGate. For example, you can export the gate signal connected
to counter 0 to the PFI 38/CTR 0 GATE pin, even if another PFI is inputting
the Ctr0Gate signal. This output is set to high-impedance at startup.
Figure 3-5 shows the timing requirements for the CtrnGate signal.
CtrnGate
Figure 3-5. Timing Requirements for CtrnGate Signal
The minimum pulse width and period listed in Table 3-6 is the minimum
required for the internal signals. The TIO device has signal requirements in
order to pass through the isolation circuitry. For more information about
these signal requirements, refer to the NI 660x Specifications document,
available for download from
Table 3-6. Minimum Pulse Width for CtrnGate Internal Signals
Minimum with
Minimum RTSI Connector
5 ns
Tgatepw
ni.com/manuals
5 ns CtrnGate minimum pulse width
3-13
Chapter 3 Signal Connections
Tgatepw
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Description
NI 660x User Manual