ASROCK H510M-H/M.2 SE Setup Manual page 29

H510M-H/M.2 SE
RAS# Active Time (tRAS)
The number of clock cycles required between a bank active command and issuing the
precharge command.
Command Rate (CR)
The delay between when a memory chip is selected and when the first active command can
be issued.
Secondary Timing
Write Recovery Time (tWR)
The amount of delay that must elapse after the completion of a valid write operation, before
an active bank can be precharged.
Refresh Cycle Time (tRFC)
The number of clocks from a Refresh command until the first Activate command to the
same rank.
RAS to RAS Delay (tRRD_L)
The number of clocks between two rows activated in different banks of the same rank.
RAS to RAS Delay (tRRD_S)
The number of clocks between two rows activated in different banks of the same rank.
Write to Read Delay (tWTR_L)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre-charge
command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
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