Pioneer DVL-90 Service Manual page 117

DVL-90, DVL-700
111] RSTB |__| Reset input for IC as a whole. The built-in register,
PORT2 fo
circuitry, etc. will be initialized when the system is set to "L".
is GND ______| =| Grounding terminal, Comec'to GND (GND ofihelogic gwen). ——=—SCS~C~—"S~CS*SC—C"'—'"'"'"'"'"'<;<CSCS*?
SPD2 IO | Data input/output of DRAM for subvideo. Connect to data input/output of 256 kii~4 bits DRAM.
119] SPDO__——*d
[120| SPWEB | 0 | TWE output to DRAM for subvideo. Connect to the [WE terminal of 256154 bis DRAM SSS
[i2i| SPRASB | 0_| RAS output to DRAM for subvideo. Connect tothe RAS terminal of 256154 bits DRAM. __——SS——=S
[122| SPCASB____| 0" | /CAS output to DRAM for subvideo. Connect tothe [CAS terminal of 25654 bits DRAM. ____———SS—S—S
[133] SPOEB | 0 | OE output to DRAM for subvideo. Connect tothe /OE terminal of 256 k54 bis DRAM.————SS——id
fi24| VDD | -_| Power terminal. Connect 10 +3.3V (WDDofihelogicsystem. SSCS
1 2 5 [ G N D _ _ _ _ _ _ _ | -_| Grounding terminal. Conneat to GND (GND of te logicsystem) SSS
26 | SPAS
127 | SPAT
128 | SPA6
129 | SPAS
SPA4
riar| spas
f135| VDD] ~__| Power terminal. Connectto «3.3 V (VDD of the ogiosystem)__——=—SSCSCSCSCSCSCSCSCSCSCSCSCTTC~CS
136[GND______| = | Grounding terminal. Connect to GND (GND of he logicsystems). SSCS
F137 CR27MO | 0 | 27 MHz clock output from built-in Xtal OSC. The terminal i buffered, and can drive external Grout ——————=
[138| CK27MI | I_[ 27 MHZ system clock input during external input mode ofthis IC. Inputs rectangular wave of27MFz___————
[139[ VDD | - | Power terminal. Connect to+3.3V (VDD ofthelogicsystem) SSCS
[140| DUMMY | 0 | Dummy output of built-in X'tal OSC. Normally leaveit open. ——SSSSSSSSSCSCSCSCSCSCSSCC*d
'i4i[ XTALI | TI | Input of builtin Xtal OSC. Use the terminal by connecting the Xtal to emternal Grau ——————SSSCSC~SC
ir oi Output of built-in X'tal OSC. Use the terminal by connecting the X'tal to external. Cannot supply the clock to external
circuit from this terminal. Should use CK27MO. For the system clock of this IC, this signal is internally buffered during
1i43[GND ————s|_-_| Grounding terminal. Connect to GND (GND of the logic system).
internal input.
fi44[GND —_|_-_| Grounding terminal. Connect to GND (GND of the logic system).
Outputs the content of the built-in register of the same name.
=
Address output of DRAM for subvideo. Connect to address output of 256 k54 bits DRAM. SPAQ is LSB, and SPA8 is
MSB.
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